0a6a1f1d05
This brings our tree to NetBSD 7.0, as found on -current on the 10-10-2015. This updates: - LLVM to 3.6.1 - GCC to GCC 5.1 - Replace minix/commands/zdump with usr.bin/zdump - external/bsd/libelf has moved to /external/bsd/elftoolchain/ - Import ctwm - Drop sprintf from libminc Change-Id: I149836ac18e9326be9353958bab9b266efb056f0
112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
// RUN: %clang_cc1 -O3 -triple arm64-apple-ios7 -target-feature +neon -S -ffreestanding %s -o - -target-cpu cyclone | FileCheck %s
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// REQUIRES: aarch64-registered-target
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// test code generation for <rdar://problem/11487757>
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#include <arm_neon.h>
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unsigned bar();
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// Branch if any lane of V0 is zero; 64 bit => !min
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unsigned anyZero64(uint16x4_t a) {
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// CHECK: anyZero64:
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// CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: b {{_bar|bar}}
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if (!vminv_u8(a))
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return bar();
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return 0;
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}
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// Branch if any lane of V0 is zero; 128 bit => !min
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unsigned anyZero128(uint16x8_t a) {
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// CHECK: anyZero128:
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// CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: b {{_bar|bar}}
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if (!vminvq_u8(a))
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return bar();
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return 0;
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}
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// Branch if any lane of V0 is non-zero; 64 bit => max
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unsigned anyNonZero64(uint16x4_t a) {
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// CHECK: anyNonZero64:
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// CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: movz w0, #0
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if (vmaxv_u8(a))
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return bar();
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return 0;
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}
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// Branch if any lane of V0 is non-zero; 128 bit => max
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unsigned anyNonZero128(uint16x8_t a) {
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// CHECK: anyNonZero128:
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// CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: movz w0, #0
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if (vmaxvq_u8(a))
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return bar();
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return 0;
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}
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// Branch if all lanes of V0 are zero; 64 bit => !max
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unsigned allZero64(uint16x4_t a) {
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// CHECK: allZero64:
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// CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: b {{_bar|bar}}
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if (!vmaxv_u8(a))
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return bar();
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return 0;
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}
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// Branch if all lanes of V0 are zero; 128 bit => !max
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unsigned allZero128(uint16x8_t a) {
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// CHECK: allZero128:
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// CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: b {{_bar|bar}}
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if (!vmaxvq_u8(a))
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return bar();
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return 0;
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}
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// Branch if all lanes of V0 are non-zero; 64 bit => min
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unsigned allNonZero64(uint16x4_t a) {
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// CHECK: allNonZero64:
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// CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: movz w0, #0
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if (vminv_u8(a))
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return bar();
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return 0;
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}
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// Branch if all lanes of V0 are non-zero; 128 bit => min
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unsigned allNonZero128(uint16x8_t a) {
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// CHECK: allNonZero128:
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// CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
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// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]]
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// CHECK: [[LABEL]]:
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// CHECK-NEXT: movz w0, #0
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if (vminvq_u8(a))
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return bar();
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return 0;
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}
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