f7df02e747
This is a driver-breaking update to the netdriver library, which is
used by all network drivers. The aim of this change is to make the
library more compatible with NetBSD, and in particular with various
features that are expected to be supported by the NetBSD userland.
The main changes made by this patch are the following:
- each network driver now has a NetBSD-style short device name;
- drivers are not expected to receive packets right after startup;
- extended support for receipt modes, including multicast lists;
- support for multiple parallel send, receive requests;
- embedding of I/O vectors in send and receive requests;
- support for capabilities, including checksum offloading;
- support for reporting link status updates to the TCP/IP stack;
- support for setting and retrieving media status;
- support for changing the hardware (MAC) address;
- support for NetBSD interface flags IFF_DEBUG, IFF_LINK[0-2];
- support for NetBSD error statistics;
- support for regular time-based ("tick") callbacks.
IMPORTANT: this patch applies a minimal update to the existing drivers
in order to make them work at all with the new netdriver library. It
however does *not* change all drivers to make use of the new features.
In fact, strictly speaking, all drivers are now violating requirements
imposed by the new library in one way or another, most notably by
enabling packet receipt when starting the driver. Changing all the
drivers to be compliant, and to support the newly added options, is
left to future patches. The existing drivers should currently *not*
be taken as examples of how to implement a new network driver!
With that said, a few drivers have already been changed to make use of
some of the new features: fxp, e1000, rtl8139, and rtl8169 now report
link and media status, and the last three of those now support setting
the hardware MAC address on the fly. In addition, dp8390 has been
changed to default to PCI autoconfiguration if no configuration is
specified through environment variables.
Change-Id: I4b3ea9c0b9bc25d5b0609c6ff256fb0db71cdc42
196 lines
9.5 KiB
C
196 lines
9.5 KiB
C
/* 3Com 3C90xB/C EtherLink driver, by D.C. van Moolenbroek */
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#ifndef _DRIVERS_NET_3C90X_H
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#define _DRIVERS_NET_3C90X_H
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/* The following time values are in microseconds (us). */
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#define XLBC_CMD_TIMEOUT 1000 /* command timeout */
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#define XLBC_EEPROM_TIMEOUT 500 /* EEPROM read timeout */
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#define XLBC_AUTONEG_TIMEOUT 2000000 /* auto-negotiation timeout */
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#define XLBC_RESET_DELAY 1000 /* wait time for reset */
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#define XLBC_MII_DELAY 1 /* MII cycle response time */
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/*
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* Transmission and receipt memory parameters. The current values allow for
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* buffering of about 32 full-size packets, requiring 48KB of memory for each
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* direction (and thus 96KB in total). For transmission, it is possible to
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* queue many more small packets using the same memory area. For receipt, it
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* is not, since each incoming packet may be of full size. This explains the
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* seemingly huge difference in descriptor counts.
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*/
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#define XLBC_DPD_COUNT 256 /* TX descriptor count */
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#define XLBC_TXB_SIZE 48128 /* TX buffer size in bytes */
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#define XLBC_UPD_COUNT 32 /* RX descriptor count */
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#define XLBC_MIN_PKT_LEN NDEV_ETH_PACKET_MIN
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#define XLBC_MAX_PKT_LEN NDEV_ETH_PACKET_MAX_TAGGED
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#define XLBC_MIN_REG_SIZE 128 /* min. register memory size */
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#define XLBC_CMD_REG 0x0e /* command register */
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# define XLBC_CMD_GLOBAL_RESET 0x0000 /* perform overall NIC reset */
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# define XLBC_CMD_RX_RESET 0x2800 /* perform receiver reset */
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# define XLBC_CMD_TX_RESET 0x5800 /* perform transmitter reset */
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# define XLBC_CMD_DN_STALL 0x3002 /* stall download */
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# define XLBC_CMD_DN_UNSTALL 0x3003 /* unstall download */
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# define XLBC_CMD_TX_ENABLE 0x4800 /* enable transmission */
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# define XLBC_CMD_RX_ENABLE 0x2000 /* enable receipt */
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# define XLBC_CMD_SET_FILTER 0x8000 /* set receipt filter */
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# define XLBC_CMD_UP_UNSTALL 0x3001 /* unstall upload */
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# define XLBC_CMD_IND_ENABLE 0x7800 /* enable indications */
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# define XLBC_CMD_INT_ENABLE 0x7000 /* enable interrupts */
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# define XLBC_CMD_SELECT_WINDOW 0x0800 /* select register window */
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# define XLBC_CMD_STATS_ENABLE 0xa800 /* enable statistics */
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#define XLBC_FILTER_STATION 0x01 /* packets addressed to NIC */
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#define XLBC_FILTER_MULTI 0x02 /* multicast packets */
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#define XLBC_FILTER_BROAD 0x04 /* broadcast packets */
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#define XLBC_FILTER_PROMISC 0x08 /* all packets (promiscuous) */
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#define XLBC_STATUS_REG 0x0e /* interupt status register */
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# define XLBC_STATUS_HOST_ERROR 0x0002 /* catastrophic host error */
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# define XLBC_STATUS_TX_COMPLETE 0x0004 /* packet transmission done */
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# define XLBC_STATUS_UPDATE_STATS 0x0080 /* statistics need retrieval */
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# define XLBC_STATUS_LINK_EVENT 0x0100 /* link status change event */
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# define XLBC_STATUS_DN_COMPLETE 0x0200 /* packet download completed */
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# define XLBC_STATUS_UP_COMPLETE 0x0400 /* packet upload completed */
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# define XLBC_STATUS_IN_PROGRESS 0x1000 /* command still in progress */
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/* The mask of interrupts in which we are interested. */
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#define XLBC_STATUS_MASK \
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(XLBC_STATUS_HOST_ERROR | \
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XLBC_STATUS_TX_COMPLETE | \
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XLBC_STATUS_UPDATE_STATS | \
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XLBC_STATUS_LINK_EVENT | \
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XLBC_STATUS_DN_COMPLETE | \
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XLBC_STATUS_UP_COMPLETE)
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#define XLBC_TX_STATUS_REG 0x1b /* TX status register */
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# define XLBC_TX_STATUS_OVERFLOW 0x04 /* TX status stack full */
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# define XLBC_TX_STATUS_MAX_COLL 0x08 /* max collisions reached */
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# define XLBC_TX_STATUS_UNDERRUN 0x10 /* packet transfer underrun */
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# define XLBC_TX_STATUS_JABBER 0x20 /* transmitting for too long */
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# define XLBC_TX_STATUS_COMPLETE 0x80 /* register contents valid */
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#define XLBC_STATUS_AUTO_REG 0x1e /* auto interrupt status reg */
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#define XLBC_DMA_CTRL_REG 0x20 /* DMA control register */
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# define XLBC_DMA_CTRL_DN_INPROG 0x00000080 /* dn in progress */
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# define XLBC_DMA_CTRL_UP_NOALT 0x00010000 /* disable up altseq */
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# define XLBC_DMA_CTRL_DN_NOALT 0x00020000 /* disable dn altseq */
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#define XLBC_DN_LIST_PTR_REG 0x24 /* download pointer register */
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#define XLBC_UP_LIST_PTR_REG 0x38 /* uplist pointer register */
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#define XLBC_EEPROM_WINDOW 0 /* EEPROM register window */
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#define XLBC_EEPROM_CMD_REG 0x0a /* EEPROM command register */
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# define XLBC_EEPROM_CMD_ADDR 0x003f /* address mask */
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# define XLBC_EEPROM_CMD_READ 0x0080 /* read register opcode */
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# define XLBC_EEPROM_CMD_BUSY 0x8000 /* command in progress */
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#define XLBC_EEPROM_DATA_REG 0x0c /* EEPROM data register */
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#define XLBC_EEPROM_WORD_OEM_ADDR0 0x0a /* OEM node address, word 0 */
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#define XLBC_EEPROM_WORD_OEM_ADDR1 0x0b /* OEM node address, word 1 */
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#define XLBC_EEPROM_WORD_OEM_ADDR2 0x0c /* OEM node address, word 2 */
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#define XLBC_STATION_WINDOW 2 /* station register window */
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#define XLBC_STATION_ADDR0_REG 0x00 /* station address, word 0 */
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#define XLBC_STATION_ADDR1_REG 0x02 /* station address, word 1 */
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#define XLBC_STATION_ADDR2_REG 0x04 /* station address, word 2 */
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#define XLBC_STATION_MASK0_REG 0x06 /* station mask, word 0 */
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#define XLBC_STATION_MASK1_REG 0x08 /* station mask, word 1 */
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#define XLBC_STATION_MASK2_REG 0x0a /* station mask, word 2 */
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#define XLBC_CONFIG_WINDOW 3 /* configuration window */
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#define XLBC_CONFIG_WORD1_REG 0x02 /* high-order 16 config bits */
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# define XLBC_CONFIG_XCVR_MASK 0x00f0 /* transceiver selection */
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# define XLBC_CONFIG_XCVR_AUTO 0x0080 /* auto-negotiation */
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#define XLBC_MAC_CTRL_WINDOW 3 /* MAC control window */
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#define XLBC_MAC_CTRL_REG 0x06 /* MAC control register */
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# define XLBC_MAC_CTRL_ENA_FD 0x0020 /* enable full duplex */
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#define XLBC_MEDIA_OPT_WINDOW 3 /* media options window */
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#define XLBC_MEDIA_OPT_REG 0x08 /* media options register */
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# define XLBC_MEDIA_OPT_BASE_TX 0x0002 /* 100BASE-TX available */
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# define XLBC_MEDIA_OPT_10_BT 0x0008 /* 10BASE-T available */
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#define XLBC_NET_DIAG_WINDOW 4 /* net diagnostics window */
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#define XLBC_NET_DIAG_REG 0x06 /* net diagnostics register */
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# define XLBC_NET_DIAG_UPPER 0x0040 /* enable upper stats bytes */
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#define XLBC_PHYS_MGMT_WINDOW 4 /* physical mgmt window */
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#define XLBC_PHYS_MGMT_REG 0x08 /* physical mgmt register */
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# define XLBC_PHYS_MGMT_CLK 0x0001 /* MII management clock */
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# define XLBC_PHYS_MGMT_DATA 0x0002 /* MII management data bit */
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# define XLBC_PHYS_MGMT_DIR 0x0004 /* MII data direction bit */
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#define XLBC_PHY_ADDR 0x18 /* internal PHY address */
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#define XLBC_MII_CONTROL 0x00 /* MII control register */
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# define XLBC_MII_CONTROL_AUTONEG 0x0200 /* restart auto-negotiation */
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# define XLBC_MII_CONTROL_RESET 0x8000 /* reset the PHY */
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#define XLBC_MII_STATUS 0x01 /* MII status register */
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# define XLBC_MII_STATUS_EXTCAP 0x0001 /* extended capability */
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# define XLBC_MII_STATUS_AUTONEG 0x0008 /* auto-neg capability */
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# define XLBC_MII_STATUS_COMPLETE 0x0020 /* auto-neg complete */
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#define XLBC_MII_AUTONEG_ADV 0x04 /* MII auto-neg advertise */
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# define XLBC_MII_LINK_T_HD 0x0020 /* 10BASE-T half-duplex */
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# define XLBC_MII_LINK_T_FD 0x0040 /* 10BASE-T full-duplex */
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# define XLBC_MII_LINK_TX_HD 0x0080 /* 100BASE-TX half-duplex */
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# define XLBC_MII_LINK_TX_FD 0x0100 /* 100BASE-TX full-duplex */
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#define XLBC_MII_LP_ABILITY 0x05 /* MII link partner ability */
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#define XLBC_MII_AUTONEG_EXP 0x06 /* MII auto-neg expansion */
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#define XLBC_MEDIA_STS_WINDOW 4 /* media status window */
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#define XLBC_MEDIA_STS_REG 0x0a /* media status register */
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# define XLBC_MEDIA_STS_LINK_DET 0x0800 /* link detected */
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# define XLBC_MEDIA_STS_TX_INPROG 0x1000 /* TX in progress */
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#define XLBC_SSD_STATS_WINDOW 4 /* SSD statistics window */
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#define XLBC_BAD_SSD_REG 0x0c /* bad start-of-stream delim */
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#define XLBC_STATS_WINDOW 6 /* statistics window */
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#define XLBC_CARRIER_LOST_REG 0x00 /* # packets w/ carrier lost */
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#define XLBC_SQE_ERR_REG 0x01 /* # SQE pulse errors */
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#define XLBC_MULTI_COLL_REG 0x02 /* # multiple collisions */
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#define XLBC_SINGLE_COLL_REG 0x03 /* # single collisions */
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#define XLBC_LATE_COLL_REG 0x04 /* # late collisions */
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#define XLBC_RX_OVERRUNS_REG 0x05 /* # receiver overruns */
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#define XLBC_FRAMES_XMIT_OK_REG 0x06 /* # frames transmitted */
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#define XLBC_FRAMES_RCVD_OK_REG 0x07 /* # frames received */
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#define XLBC_FRAMES_DEFERRED_REG 0x08 /* # frames deferred */
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#define XLBC_UPPER_FRAMES_REG 0x09 /* upper bits of frame stats */
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# define XLBC_UPPER_RX_MASK 0x03 /* mask for frames received */
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# define XLBC_UPPER_RX_SHIFT 0 /* shift for frames received */
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# define XLBC_UPPER_TX_MASK 0x30 /* mask for frames sent */
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# define XLBC_UPPER_TX_SHIFT 4 /* shift for frames sent */
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#define XLBC_BYTES_RCVD_OK_REG 0x0a /* # bytes received */
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#define XLBC_BYTES_XMIT_OK_REG 0x0c /* # bytes transmitted */
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typedef struct {
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uint32_t next; /* physical address of next descriptor */
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uint32_t flags; /* frame start header or packet status */
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uint32_t addr; /* address of first (and only) fragment */
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uint32_t len; /* length of first (and only) fragment */
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} xlbc_pd_t;
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/* Bits for the 'flags' field of download descriptors. */
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#define XLBC_DN_RNDUP_WORD 0x00000002 /* round up to word */
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#define XLBC_DN_DN_COMPLETE 0x00010000 /* download complete */
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#define XLBC_DN_DN_INDICATE 0x80000000 /* fire DN_COMPLETE */
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/* Bits for the 'flags' field of upload descriptors. */
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#define XLBC_UP_LEN 0x00001fff /* packet length */
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#define XLBC_UP_ERROR 0x00004000 /* receive error */
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#define XLBC_UP_COMPLETE 0x00008000 /* packet complete */
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#define XLBC_UP_OVERRUN 0x00010000 /* FIFO overrun */
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#define XLBC_UP_ALIGN_ERR 0x00040000 /* alignment error */
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#define XLBC_UP_CRC_ERR 0x00080000 /* CRC error */
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#define XLBC_UP_OVERFLOW 0x01000000 /* buffer too small */
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/* Bits for the 'len' field of upload and download descriptors. */
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#define XLBC_LEN_LAST 0x80000000 /* last fragment */
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#endif /* !_DRIVERS_NET_3C90X_H */
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