f7df02e747
This is a driver-breaking update to the netdriver library, which is
used by all network drivers. The aim of this change is to make the
library more compatible with NetBSD, and in particular with various
features that are expected to be supported by the NetBSD userland.
The main changes made by this patch are the following:
- each network driver now has a NetBSD-style short device name;
- drivers are not expected to receive packets right after startup;
- extended support for receipt modes, including multicast lists;
- support for multiple parallel send, receive requests;
- embedding of I/O vectors in send and receive requests;
- support for capabilities, including checksum offloading;
- support for reporting link status updates to the TCP/IP stack;
- support for setting and retrieving media status;
- support for changing the hardware (MAC) address;
- support for NetBSD interface flags IFF_DEBUG, IFF_LINK[0-2];
- support for NetBSD error statistics;
- support for regular time-based ("tick") callbacks.
IMPORTANT: this patch applies a minimal update to the existing drivers
in order to make them work at all with the new netdriver library. It
however does *not* change all drivers to make use of the new features.
In fact, strictly speaking, all drivers are now violating requirements
imposed by the new library in one way or another, most notably by
enabling packet receipt when starting the driver. Changing all the
drivers to be compliant, and to support the newly added options, is
left to future patches. The existing drivers should currently *not*
be taken as examples of how to implement a new network driver!
With that said, a few drivers have already been changed to make use of
some of the new features: fxp, e1000, rtl8139, and rtl8169 now report
link and media status, and the last three of those now support setting
the hardware MAC address on the fly. In addition, dp8390 has been
changed to default to PCI autoconfiguration if no configuration is
specified through environment variables.
Change-Id: I4b3ea9c0b9bc25d5b0609c6ff256fb0db71cdc42
178 lines
6.7 KiB
C
178 lines
6.7 KiB
C
#ifndef INCL_DEC21041_H_GUARD
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#define INCL_DEC21041_H_GUARD
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/*
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de.h
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Header for the driver of the DEC 21140A ethernet card as emulated
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by VirtualPC 2007
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Created: 09/01/2009 Nicolas Tittley (first.last @ gmail DOT com)
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*/
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#include <sys/null.h>
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#if debug == 1
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# define DEBUG(statm) statm
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#else
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# define DEBUG(statm)
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#endif
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#define DE_NB_SEND_DESCR 32
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#define DE_SEND_BUF_SIZE (NDEV_ETH_PACKET_MAX+2)
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#define DE_NB_RECV_DESCR 32
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#define DE_RECV_BUF_SIZE (NDEV_ETH_PACKET_MAX+2)
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#define DE_MIN_BASE_ADDR 0x0400
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#define DE_SROM_EA_OFFSET 20
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#define DE_SETUP_FRAME_SIZE 192
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typedef struct de_descr {
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u32_t des[4];
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} de_descr_t;
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typedef struct de_local_descr {
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de_descr_t *descr;
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u8_t *buf1;
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u8_t *buf2;
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} de_loc_descr_t;
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typedef struct dpeth {
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port_t de_base_port; /* Base port, for multiple card instance */
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int de_irq; /* IRQ line number */
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int de_hook; /* interrupt hook at kernel */
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int de_type; /* What kind of hardware */
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/* Space reservation. We will allocate all structures later in the code.
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here we just make sure we have the space we need at compile time */
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u8_t sendrecv_descr_buf[(DE_NB_SEND_DESCR+DE_NB_RECV_DESCR)*
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sizeof(de_descr_t)];
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u8_t sendrecv_buf[DE_NB_SEND_DESCR*DE_SEND_BUF_SIZE +
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DE_NB_RECV_DESCR*DE_RECV_BUF_SIZE];
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phys_bytes sendrecv_descr_phys_addr[2];
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de_loc_descr_t descr[2][MAX(DE_NB_RECV_DESCR, DE_NB_SEND_DESCR)];
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int cur_descr[2];
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#define DESCR_RECV 0
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#define DESCR_TRAN 1
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/* Serial ROM */
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#define SROM_BITWIDTH 6
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u8_t srom[((1<<SROM_BITWIDTH)-1)*2]; /* Space to read in
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all the configuration ROM */
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} dpeth_t;
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/************/
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/* Revisons */
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/************/
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#define DEC_21140A 0x20
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#define DE_TYPE_UNKNOWN 0x0
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/* #define CSR_ADDR(x, i) csraddr2(x->de_base_port + i) */
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#define CSR_ADDR(x, i) (x->de_base_port + i)
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/* CSRs */
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#define CSR0 0x00
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#define CSR0_SWR 0x00000001 /* sw reset */
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#define CSR0_BAR 0x00000002 /* bus arbitration */
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#define CSR0_CAL_8 0x00004000 /* cache align 8 long word */
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#define CSR0_TAP 0x00080000 /* trans auto polling */
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#define CSR1 0x08 /* transmit poll demand */
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#define CSR2 0x10 /* receive poll demand */
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#define CSR3 0x18 /* receive list address */
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#define CSR4 0x20 /* transmit list address */
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#define CSR5 0x28 /* status register */
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#define CSR5_EB 0x03800000 /* error bits */
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#define CSR5_TS 0x00700000 /* Transmit proc state */
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#define CSR5_RS 0x000E0000 /* Receive proc state */
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#define CSR5_NIS 0x00010000 /* Norm Int summ */
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#define CSR5_AIS 0x00008000 /* Abnorm Int sum */
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#define CSR5_FBE 0x00002000 /* Fatal bit error */
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#define CSR5_GTE 0x00000800 /* Gen-purp timer exp */
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#define CSR5_ETI 0x00000400 /* Early Trans int */
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#define CSR5_RWT 0x00000200 /* Recv watchdog timeout */
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#define CSR5_RPS 0x00000100 /* Recv proc stop */
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#define CSR5_RU 0x00000080 /* Recv buf unavail */
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#define CSR5_RI 0x00000040 /* Recv interrupt */
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#define CSR5_UNF 0x00000020 /* Trans underflow */
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#define CSR5_TJT 0x00000008 /* Trans Jabber Timeout */
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#define CSR5_TU 0x00000004 /* Trans buf unavail */
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#define CSR5_TPS 0x00000002 /* Trans proc stopped */
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#define CSR5_TI 0x00000001 /* Trans interrupt */
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#define CSR6 0x30 /* Operation mode */
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#define CSR6_SC 0x80000000 /* Special capt effect ena 31 */
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#define CSR6_RA 0x40000000 /* receive all 30 */
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#define CSR6_MBO 0x02000000 /* must be one 25 */
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#define CSR6_SCR 0x01000000 /* Scrambler mode 24 */
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#define CSR6_PCS 0x00800000 /* PCS function 23 */
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#define CSR6_TTM 0x00400000 /* Trans threshold mode 22 */
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#define CSR6_SF 0x00200000 /* store and forward 21 */
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#define CSR6_HBD 0x00080000 /* Heartbeat disable 19 */
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#define CSR6_PS 0x00040000 /* port select 18 */
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#define CSR6_CA 0x00020000 /* Capt effect ena 17 */
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#define CSR6_TR_00 0x00000000 /* Trans thresh 15:14 */
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#define CSR6_TR_01 0x00004000 /* Trans thresh 15:14 */
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#define CSR6_TR_10 0x00008000 /* Trans thresh 15:14 */
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#define CSR6_TR_11 0x0000C000 /* Trans thresh 15:14 */
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#define CSR6_ST 0x00002000 /* start/stop trans 13 */
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#define CSR6_FD 0x00000200 /* Full Duplex 9 */
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#define CSR6_PM 0x00000080 /* Pass all multicast 7 */
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#define CSR6_PR 0x00000040 /* Promisc mode 6 */
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#define CSR6_IF 0x00000010 /* Inv filtering 4 */
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#define CSR6_HO 0x00000004 /* Hash-only filtering 2 */
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#define CSR6_SR 0x00000002 /* start/stop recv 1 */
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#define CSR6_HP 0x00000001 /* Hash/perfect recv filt mode 0 */
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#define CSR7 0x38 /* Interrupt enable */
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#define CSR7_NI 0x00010000 /* Normal interrupt ena */
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#define CSR7_AI 0x00008000 /* Abnormal int ena */
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#define CSR7_TI 0x00000001 /* trans int ena */
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#define CSR7_TU 0x00000004 /* trans buf unavail ena */
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#define CSR7_RI 0x00000040 /* recv interp ena */
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#define CSR7_GPT 0x00000800 /* gen purpose timer ena */
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#define CSR9 0x48 /* Boot Rom, serial ROM, MII */
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#define CSR9_SR 0x0800 /* serial ROM select */
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#define CSR9_RD 0x4000 /* read */
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#define CSR9_DO 0x0008 /* data out */
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#define CSR9_DI 0x0004 /* data in */
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#define CSR9_SRC 0x0002 /* serial clock */
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#define CSR9_CS 0x0001 /* serial rom chip select */
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/* Send/Recv Descriptors */
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#define DES0 0
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#define DES0_OWN 0x80000000 /* descr ownership. 1=211140A */
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#define DES0_FL 0x3FFF0000 /* frame length */
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#define DES0_FL_SHIFT 16 /* shift to fix frame length */
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#define DES0_ES 0x00008000 /* Error sum */
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#define DES0_TO 0x00004000 /* Trans jabber timeout */
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#define DES0_LO 0x00000800 /* Loss of carrier */
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#define DES0_NC 0x00000400 /* no carrier */
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#define DES0_LC 0x00000200 /* Late coll */
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#define DES0_EC 0x00000100 /* Excessive coll */
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#define DES0_UF 0x00000002 /* Underflow error */
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#define DES0_RE 0x00000008 /* MII error */
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#define DES0_FS 0x00000200 /* first descr */
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#define DES0_LS 0x00000100 /* last descr */
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#define DES1 1
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#define DES1_ER 0x02000000 /* end of ring */
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#define DES1_SAC 0x01000000 /* 2nd address chained */
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#define DES1_BS2 0x003FF800 /* 2nd buffer size */
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#define DES1_BS2_SHFT 11 /* shift to obtain 2nd buffer size */
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#define DES1_BS1 0x000007FF /* 1nd buffer size */
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#define DES1_IC 0x80000000 /* Interrupt on completion 31 */
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#define DES1_LS 0x40000000 /* Last Segment 30 */
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#define DES1_FS 0x20000000 /* First Segment 29 */
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#define DES1_FT1 0x10000000 /* Filtering type 28 */
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#define DES1_SET 0x08000000 /* Setup frame 27 */
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#define DES1_AC 0x04000000 /* Add CRC disable 26 */
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#define DES1_DPD 0x00800000 /* Disabled padding 23 */
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#define DES1_FT0 0x00400000 /* Filtering type 22 */
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#define DES2 2 /* 1st buffer addr */
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#define DES3 3 /* 2nd buffer addr */
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#define DES_BUF1 DES2
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#define DES_BUF2 DES3
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#endif /* Include Guard */
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