132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
/*
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pci.h
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Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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*/
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/* tempory functions: to be replaced later (see pci_intel.h) */
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_PROTOTYPE( unsigned pci_inb, (U16_t port) );
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_PROTOTYPE( unsigned pci_inw, (U16_t port) );
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_PROTOTYPE( unsigned pci_inl, (U16_t port) );
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_PROTOTYPE( void pci_outb, (U16_t port, U8_t value) );
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_PROTOTYPE( void pci_outw, (U16_t port, U16_t value) );
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_PROTOTYPE( void pci_outl, (U16_t port, U32_t value) );
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/* pci.c */
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_PROTOTYPE( void pci_init, (void) );
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_PROTOTYPE( int pci_find_dev, (U8_t bus, U8_t dev, U8_t func,
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int *devindp) );
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_PROTOTYPE( int pci_first_dev, (int *devindp, u16_t *vidp, u16_t *didp) );
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_PROTOTYPE( int pci_next_dev, (int *devindp, u16_t *vidp, u16_t *didp) );
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_PROTOTYPE( void pci_reserve, (int devind) );
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_PROTOTYPE( void pci_ids, (int devind, u16_t *vidp, u16_t *didp) );
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_PROTOTYPE( char *pci_slot_name, (int devind) );
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_PROTOTYPE( char *pci_dev_name, (U16_t vid, U16_t did) );
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_PROTOTYPE( u8_t pci_attr_r8, (int devind, int port) );
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_PROTOTYPE( u16_t pci_attr_r16, (int devind, int port) );
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_PROTOTYPE( u32_t pci_attr_r32, (int devind, int port) );
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_PROTOTYPE( void pci_attr_w16, (int devind, int port, U16_t value) );
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_PROTOTYPE( void pci_attr_w32, (int devind, int port, u32_t value) );
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#define PCI_VID 0x00 /* Vendor ID, 16-bit */
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#define PCI_DID 0x02 /* Device ID, 16-bit */
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#define PCI_CR 0x04 /* Command Register, 16-bit */
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#define PCI_PCISTS 0x06 /* PCI status, 16-bit */
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#define PSR_SSE 0x4000 /* Signaled System Error */
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#define PSR_RMAS 0x2000 /* Received Master Abort Status */
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#define PSR_RTAS 0x1000 /* Received Target Abort Status */
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#define PCI_REV 0x08 /* Revision ID */
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#define PCI_PIFR 0x09 /* Prog. Interface Register */
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#define PCI_SCR 0x0A /* Sub-Class Register */
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#define PCI_BCR 0x0B /* Base-Class Register */
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#define PCI_HEADT 0x0E /* Header type, 8-bit */
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#define PHT_MULTIFUNC 0x80 /* Multiple functions */
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#define PCI_BAR 0x10 /* Base Address Register */
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#define PCI_BAR_2 0x14 /* Base Address Register */
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#define PCI_BAR_3 0x18 /* Base Address Register */
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#define PCI_BAR_4 0x1C /* Base Address Register */
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#define PCI_ILR 0x3C /* Interrupt Line Register */
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#define PCI_IPR 0x3D /* Interrupt Pin Register */
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/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */
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#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */
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#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */
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/* PCI bridge devices (AGP) */
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#define PPB_SBUSN 0x19 /* Secondary Bus Number */
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/* Intel compatible PCI bridge devices (AGP) */
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#define PPB_SSTS 0x1E /* Secondary PCI-to-PCI Status Register */
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#define NO_VID 0xffff /* No PCI card present */
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struct pci_vendor
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{
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u16_t vid;
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char *name;
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};
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struct pci_device
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{
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u16_t vid;
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u16_t did;
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char *name;
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};
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struct pci_baseclass
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{
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u8_t baseclass;
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char *name;
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};
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struct pci_subclass
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{
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u8_t baseclass;
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u8_t subclass;
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u16_t infclass;
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char *name;
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};
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struct pci_intel_ctrl
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{
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u16_t vid;
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u16_t did;
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};
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struct pci_isabridge
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{
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u16_t vid;
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u16_t did;
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int checkclass;
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int type;
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};
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struct pci_pcibridge
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{
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u16_t vid;
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u16_t did;
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int type;
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};
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#define PCI_IB_PIIX 1 /* Intel PIIX compatible ISA bridge */
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#define PCI_IB_VIA 2 /* VIA compatible ISA bridge */
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#define PCI_IB_AMD 3 /* AMD compatible ISA bridge */
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#define PCI_IB_SIS 4 /* SIS compatible ISA bridge */
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#define PCI_PCIB_INTEL 1 /* Intel compatible PCI bridge */
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#define PCI_AGPB_INTEL 2 /* Intel compatible AGP bridge */
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#define PCI_AGPB_VIA 3 /* VIA compatible AGP bridge */
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extern struct pci_vendor pci_vendor_table[];
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extern struct pci_device pci_device_table[];
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extern struct pci_baseclass pci_baseclass_table[];
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extern struct pci_subclass pci_subclass_table[];
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extern struct pci_intel_ctrl pci_intel_ctrl[];
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extern struct pci_isabridge pci_isabridge[];
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extern struct pci_pcibridge pci_pcibridge[];
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/*
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* $PchId: pci.h,v 1.4 2001/12/06 20:21:22 philip Exp $
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*/
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