2259 lines
54 KiB
C
2259 lines
54 KiB
C
#define USER_SPACE 1
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/*
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pci.c
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Configure devices on the PCI bus
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Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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*/
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#include "../drivers.h"
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#define NDEBUG /* disable assertions */
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#include <assert.h>
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#include <ibm/pci.h>
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#include <sys/vm.h>
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#include <minix/com.h>
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#include <minix/syslib.h>
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#include "pci.h"
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#include "pci_amd.h"
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#include "pci_intel.h"
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#include "pci_sis.h"
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#include "pci_via.h"
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#if __minix_vmd
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#include "config.h"
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#endif
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#if !__minix_vmd
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#define irq_mode_pci(irq) ((void)0)
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <minix/sysutil.h>
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#define NR_PCIBUS 4
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#define NR_PCIDEV 40
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#define PBT_INTEL_HOST 1
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#define PBT_PCIBRIDGE 2
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#define PBT_CARDBUS 3
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#define BAM_NR 6 /* Number of base-address registers */
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PRIVATE int debug= 0;
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PRIVATE struct pcibus
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{
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int pb_type;
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int pb_needinit;
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int pb_isabridge_dev;
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int pb_isabridge_type;
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int pb_devind;
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int pb_busnr;
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u8_t (*pb_rreg8)(int busind, int devind, int port);
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u16_t (*pb_rreg16)(int busind, int devind, int port);
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u32_t (*pb_rreg32)(int busind, int devind, int port);
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void (*pb_wreg8)(int busind, int devind, int port, U8_t value);
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void (*pb_wreg16)(int busind, int devind, int port, U16_t value);
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void (*pb_wreg32)(int busind, int devind, int port, u32_t value);
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u16_t (*pb_rsts)(int busind);
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void (*pb_wsts)(int busind, U16_t value);
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} pcibus[NR_PCIBUS];
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PRIVATE int nr_pcibus= 0;
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PRIVATE struct pcidev
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{
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u8_t pd_busnr;
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u8_t pd_dev;
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u8_t pd_func;
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u8_t pd_baseclass;
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u8_t pd_subclass;
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u8_t pd_infclass;
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u16_t pd_vid;
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u16_t pd_did;
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u8_t pd_ilr;
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u8_t pd_inuse;
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struct bar
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{
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int pb_flags;
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int pb_nr;
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u32_t pb_base;
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u32_t pb_size;
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} pd_bar[BAM_NR];
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int pd_bar_nr;
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char pd_name[M3_STRING];
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} pcidev[NR_PCIDEV];
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/* pb_flags */
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#define PBF_IO 1 /* I/O else memory */
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#define PBF_INCOMPLETE 2 /* not allocated */
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PRIVATE int nr_pcidev= 0;
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/* Work around the limitations of the PCI emulation in QEMU 0.7.1 */
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PRIVATE int qemu_pci= 0;
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FORWARD _PROTOTYPE( void pci_intel_init, (void) );
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FORWARD _PROTOTYPE( void probe_bus, (int busind) );
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FORWARD _PROTOTYPE( int is_duplicate, (U8_t busnr, U8_t dev, U8_t func) );
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FORWARD _PROTOTYPE( void record_irq, (int devind) );
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FORWARD _PROTOTYPE( void record_bars, (int devind) );
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FORWARD _PROTOTYPE( void record_bars_bridge, (int devind) );
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FORWARD _PROTOTYPE( void record_bars_cardbus, (int devind) );
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FORWARD _PROTOTYPE( void record_bar, (int devind, int bar_nr) );
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FORWARD _PROTOTYPE( void complete_bridges, (void) );
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FORWARD _PROTOTYPE( void complete_bars, (void) );
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FORWARD _PROTOTYPE( void update_bridge4dev_io, (int devind,
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u32_t io_base, u32_t io_size) );
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FORWARD _PROTOTYPE( int get_freebus, (void) );
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FORWARD _PROTOTYPE( int do_isabridge, (int busind) );
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FORWARD _PROTOTYPE( void do_pcibridge, (int busind) );
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FORWARD _PROTOTYPE( int get_busind, (int busnr) );
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FORWARD _PROTOTYPE( int do_piix, (int devind) );
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FORWARD _PROTOTYPE( int do_amd_isabr, (int devind) );
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FORWARD _PROTOTYPE( int do_sis_isabr, (int devind) );
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FORWARD _PROTOTYPE( int do_via_isabr, (int devind) );
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FORWARD _PROTOTYPE( char *pci_vid_name, (U16_t vid) );
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FORWARD _PROTOTYPE( char *pci_baseclass_name, (U8_t baseclass) );
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FORWARD _PROTOTYPE( char *pci_subclass_name, (U8_t baseclass,
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U8_t subclass, U8_t infclass) );
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FORWARD _PROTOTYPE( void ntostr, (unsigned n, char **str, char *end) );
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FORWARD _PROTOTYPE( u16_t pci_attr_rsts, (int devind) );
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FORWARD _PROTOTYPE( void pci_attr_wsts, (int devind, U16_t value) );
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FORWARD _PROTOTYPE( u16_t pcibr_std_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcibr_std_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( u16_t pcibr_cb_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcibr_cb_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( u16_t pcibr_via_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcibr_via_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( u8_t pcii_rreg8, (int busind, int devind, int port) );
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FORWARD _PROTOTYPE( u16_t pcii_rreg16, (int busind, int devind,
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int port) );
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FORWARD _PROTOTYPE( u32_t pcii_rreg32, (int busind, int devind,
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int port) );
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FORWARD _PROTOTYPE( void pcii_wreg8, (int busind, int devind, int port,
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U8_t value) );
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FORWARD _PROTOTYPE( void pcii_wreg16, (int busind, int devind, int port,
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U16_t value) );
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FORWARD _PROTOTYPE( void pcii_wreg32, (int busind, int devind, int port,
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u32_t value) );
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FORWARD _PROTOTYPE( u16_t pcii_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcii_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( void print_capabilities, (int devind) );
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/*===========================================================================*
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* helper functions for I/O *
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*===========================================================================*/
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PUBLIC unsigned pci_inb(U16_t port) {
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u32_t value;
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int s;
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if ((s=sys_inb(port, &value)) !=OK)
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printf("PCI: warning, sys_inb failed: %d\n", s);
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return value;
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}
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PUBLIC unsigned pci_inw(U16_t port) {
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u32_t value;
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int s;
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if ((s=sys_inw(port, &value)) !=OK)
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printf("PCI: warning, sys_inw failed: %d\n", s);
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return value;
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}
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PUBLIC unsigned pci_inl(U16_t port) {
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U32_t value;
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int s;
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if ((s=sys_inl(port, &value)) !=OK)
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printf("PCI: warning, sys_inl failed: %d\n", s);
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return value;
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}
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PUBLIC void pci_outb(U16_t port, U8_t value) {
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int s;
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if ((s=sys_outb(port, value)) !=OK)
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printf("PCI: warning, sys_outb failed: %d\n", s);
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}
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PUBLIC void pci_outw(U16_t port, U16_t value) {
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int s;
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if ((s=sys_outw(port, value)) !=OK)
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printf("PCI: warning, sys_outw failed: %d\n", s);
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}
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PUBLIC void pci_outl(U16_t port, U32_t value) {
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int s;
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if ((s=sys_outl(port, value)) !=OK)
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printf("PCI: warning, sys_outl failed: %d\n", s);
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}
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/*===========================================================================*
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* pci_init *
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*===========================================================================*/
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PUBLIC void pci_init()
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{
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static int first_time= 1;
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long v;
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if (!first_time)
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return;
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v= 0;
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env_parse("qemu_pci", "d", 0, &v, 0, 1);
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qemu_pci= v;
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v= 0;
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env_parse("pci_debug", "d", 0, &v, 0, 1);
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debug= v;
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/* We don't expect to interrupted */
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assert(first_time == 1);
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first_time= -1;
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/* Only Intel (compatible) PCI controllers are supported at the
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* moment.
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*/
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pci_intel_init();
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first_time= 0;
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}
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/*===========================================================================*
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* pci_find_dev *
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*===========================================================================*/
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PUBLIC int pci_find_dev(bus, dev, func, devindp)
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u8_t bus;
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u8_t dev;
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u8_t func;
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int *devindp;
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{
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int devind;
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for (devind= 0; devind < nr_pcidev; devind++)
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{
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if (pcidev[devind].pd_busnr == bus &&
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pcidev[devind].pd_dev == dev &&
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pcidev[devind].pd_func == func)
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{
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break;
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}
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}
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if (devind >= nr_pcidev)
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return 0;
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if (pcidev[devind].pd_inuse)
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return 0;
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*devindp= devind;
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return 1;
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}
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/*===========================================================================*
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* pci_first_dev *
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*===========================================================================*/
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PUBLIC int pci_first_dev(devindp, vidp, didp)
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int *devindp;
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u16_t *vidp;
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u16_t *didp;
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{
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int devind;
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for (devind= 0; devind < nr_pcidev; devind++)
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{
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if (!pcidev[devind].pd_inuse)
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break;
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}
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if (devind >= nr_pcidev)
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return 0;
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*devindp= devind;
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*vidp= pcidev[devind].pd_vid;
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*didp= pcidev[devind].pd_did;
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return 1;
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}
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/*===========================================================================*
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* pci_next_dev *
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*===========================================================================*/
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PUBLIC int pci_next_dev(devindp, vidp, didp)
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int *devindp;
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u16_t *vidp;
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u16_t *didp;
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{
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int devind;
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for (devind= *devindp+1; devind < nr_pcidev; devind++)
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{
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if (!pcidev[devind].pd_inuse)
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break;
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}
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if (devind >= nr_pcidev)
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return 0;
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*devindp= devind;
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*vidp= pcidev[devind].pd_vid;
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*didp= pcidev[devind].pd_did;
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return 1;
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}
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/*===========================================================================*
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* pci_reserve3 *
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*===========================================================================*/
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PUBLIC void pci_reserve3(devind, proc, name)
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int devind;
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int proc;
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char *name;
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{
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int i, r;
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u8_t ilr;
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struct io_range ior;
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struct mem_range mr;
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assert(devind <= nr_pcidev);
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assert(!pcidev[devind].pd_inuse);
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pcidev[devind].pd_inuse= 1;
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strcpy(pcidev[devind].pd_name, name);
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for (i= 0; i<pcidev[devind].pd_bar_nr; i++)
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{
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if (pcidev[devind].pd_bar[i].pb_flags & PBF_INCOMPLETE)
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{
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printf("pci_reserve3: BAR %d is incomplete\n", i);
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continue;
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}
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if (pcidev[devind].pd_bar[i].pb_flags & PBF_IO)
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{
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ior.ior_base= pcidev[devind].pd_bar[i].pb_base;
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ior.ior_limit= ior.ior_base +
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pcidev[devind].pd_bar[i].pb_size-1;
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if(debug) {
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printf(
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"pci_reserve3: for proc %d, adding I/O range [0x%x..0x%x]\n",
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proc, ior.ior_base, ior.ior_limit);
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}
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r= sys_privctl(proc, SYS_PRIV_ADD_IO, 0, &ior);
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if (r != OK)
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{
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printf("sys_privctl failed for proc %d: %d\n",
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proc, r);
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}
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}
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else
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{
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mr.mr_base= pcidev[devind].pd_bar[i].pb_base;
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mr.mr_limit= mr.mr_base +
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pcidev[devind].pd_bar[i].pb_size-1;
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if(debug) {
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printf(
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"pci_reserve3: for proc %d, should add memory range [0x%x..0x%x]\n",
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proc, mr.mr_base, mr.mr_limit);
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}
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r= sys_privctl(proc, SYS_PRIV_ADD_MEM, 0, &mr);
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if (r != OK)
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{
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printf("sys_privctl failed for proc %d: %d\n",
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proc, r);
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}
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}
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}
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ilr= pcidev[devind].pd_ilr;
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if (ilr != PCI_ILR_UNKNOWN)
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{
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if(debug) printf("pci_reserve3: adding IRQ %d\n", ilr);
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r= sys_privctl(proc, SYS_PRIV_ADD_IRQ, ilr, NULL);
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if (r != OK)
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{
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printf("sys_privctl failed for proc %d: %d\n",
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proc, r);
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}
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}
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}
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/*===========================================================================*
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* pci_release *
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*===========================================================================*/
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PUBLIC void pci_release(name)
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char *name;
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{
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int i;
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for (i= 0; i<nr_pcidev; i++)
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{
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if (!pcidev[i].pd_inuse)
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continue;
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if (strcmp(pcidev[i].pd_name, name) != 0)
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continue;
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pcidev[i].pd_inuse= 0;
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}
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}
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/*===========================================================================*
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* pci_ids *
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*===========================================================================*/
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PUBLIC void pci_ids(devind, vidp, didp)
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int devind;
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u16_t *vidp;
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u16_t *didp;
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{
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assert(devind <= nr_pcidev);
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*vidp= pcidev[devind].pd_vid;
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*didp= pcidev[devind].pd_did;
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}
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/*===========================================================================*
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* pci_rescan_bus *
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*===========================================================================*/
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PUBLIC void pci_rescan_bus(busnr)
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u8_t busnr;
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{
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int busind;
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busind= get_busind(busnr);
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probe_bus(busind);
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/* Allocate bus numbers for uninitialized bridges */
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complete_bridges();
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/* Allocate I/O and memory resources for uninitialized devices */
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complete_bars();
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}
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/*===========================================================================*
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* pci_slot_name *
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*===========================================================================*/
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PUBLIC char *pci_slot_name(devind)
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int devind;
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{
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static char label[]= "ddd.ddd.ddd";
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char *end;
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char *p;
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p= label;
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end= label+sizeof(label);
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ntostr(pcidev[devind].pd_busnr, &p, end);
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*p++= '.';
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ntostr(pcidev[devind].pd_dev, &p, end);
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*p++= '.';
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ntostr(pcidev[devind].pd_func, &p, end);
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return label;
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}
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/*===========================================================================*
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* pci_dev_name *
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*===========================================================================*/
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PUBLIC char *pci_dev_name(vid, did)
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u16_t vid;
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u16_t did;
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{
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int i;
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for (i= 0; pci_device_table[i].name; i++)
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{
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if (pci_device_table[i].vid == vid &&
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pci_device_table[i].did == did)
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{
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return pci_device_table[i].name;
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}
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}
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return NULL;
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}
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/*===========================================================================*
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* pci_attr_r8 *
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*===========================================================================*/
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PUBLIC u8_t pci_attr_r8(devind, port)
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int devind;
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int port;
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{
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int busnr, busind;
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busnr= pcidev[devind].pd_busnr;
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busind= get_busind(busnr);
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return pcibus[busind].pb_rreg8(busind, devind, port);
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}
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/*===========================================================================*
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* pci_attr_r16 *
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*===========================================================================*/
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PUBLIC u16_t pci_attr_r16(devind, port)
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int devind;
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int port;
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{
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int busnr, busind;
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busnr= pcidev[devind].pd_busnr;
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busind= get_busind(busnr);
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return pcibus[busind].pb_rreg16(busind, devind, port);
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}
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/*===========================================================================*
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* pci_attr_r32 *
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*===========================================================================*/
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PUBLIC u32_t pci_attr_r32(devind, port)
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int devind;
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int port;
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{
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int busnr, busind;
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busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
return pcibus[busind].pb_rreg32(busind, devind, port);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_attr_w8 *
|
|
*===========================================================================*/
|
|
PUBLIC void pci_attr_w8(devind, port, value)
|
|
int devind;
|
|
int port;
|
|
u16_t value;
|
|
{
|
|
int busnr, busind;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
pcibus[busind].pb_wreg8(busind, devind, port, value);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_attr_w16 *
|
|
*===========================================================================*/
|
|
PUBLIC void pci_attr_w16(devind, port, value)
|
|
int devind;
|
|
int port;
|
|
u16_t value;
|
|
{
|
|
int busnr, busind;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
pcibus[busind].pb_wreg16(busind, devind, port, value);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_attr_w32 *
|
|
*===========================================================================*/
|
|
PUBLIC void pci_attr_w32(devind, port, value)
|
|
int devind;
|
|
int port;
|
|
u32_t value;
|
|
{
|
|
int busnr, busind;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
pcibus[busind].pb_wreg32(busind, devind, port, value);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_intel_init *
|
|
*===========================================================================*/
|
|
PRIVATE void pci_intel_init()
|
|
{
|
|
/* Try to detect a know PCI controller. Read the Vendor ID and
|
|
* the Device ID for function 0 of device 0.
|
|
* Two times the value 0xffff suggests a system without a (compatible)
|
|
* PCI controller.
|
|
*/
|
|
u32_t bus, dev, func;
|
|
u16_t vid, did;
|
|
int s, i, r, busind, busnr;
|
|
char *dstr;
|
|
|
|
bus= 0;
|
|
dev= 0;
|
|
func= 0;
|
|
|
|
vid= PCII_RREG16_(bus, dev, func, PCI_VID);
|
|
did= PCII_RREG16_(bus, dev, func, PCI_DID);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
|
|
if (vid == 0xffff && did == 0xffff)
|
|
return; /* Nothing here */
|
|
|
|
#if 0
|
|
for (i= 0; pci_intel_ctrl[i].vid; i++)
|
|
{
|
|
if (pci_intel_ctrl[i].vid == vid &&
|
|
pci_intel_ctrl[i].did == did)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!pci_intel_ctrl[i].vid)
|
|
{
|
|
printf("pci_intel_init (warning): unknown PCI-controller:\n"
|
|
"\tvendor %04X (%s), device %04X\n",
|
|
vid, pci_vid_name(vid), did);
|
|
}
|
|
#endif
|
|
|
|
if (nr_pcibus >= NR_PCIBUS)
|
|
panic("PCI","too many PCI busses", nr_pcibus);
|
|
busind= nr_pcibus;
|
|
nr_pcibus++;
|
|
pcibus[busind].pb_type= PBT_INTEL_HOST;
|
|
pcibus[busind].pb_needinit= 0;
|
|
pcibus[busind].pb_isabridge_dev= -1;
|
|
pcibus[busind].pb_isabridge_type= 0;
|
|
pcibus[busind].pb_devind= -1;
|
|
pcibus[busind].pb_busnr= 0;
|
|
pcibus[busind].pb_rreg8= pcii_rreg8;
|
|
pcibus[busind].pb_rreg16= pcii_rreg16;
|
|
pcibus[busind].pb_rreg32= pcii_rreg32;
|
|
pcibus[busind].pb_wreg8= pcii_wreg8;
|
|
pcibus[busind].pb_wreg16= pcii_wreg16;
|
|
pcibus[busind].pb_wreg32= pcii_wreg32;
|
|
pcibus[busind].pb_rsts= pcii_rsts;
|
|
pcibus[busind].pb_wsts= pcii_wsts;
|
|
|
|
dstr= pci_dev_name(vid, did);
|
|
if (!dstr)
|
|
dstr= "unknown device";
|
|
if (debug)
|
|
{
|
|
printf("pci_intel_init: %s (%04X/%04X)\n",
|
|
dstr, vid, did);
|
|
}
|
|
|
|
probe_bus(busind);
|
|
|
|
r= do_isabridge(busind);
|
|
if (r != OK)
|
|
{
|
|
busnr= pcibus[busind].pb_busnr;
|
|
|
|
/* Disable all devices for this bus */
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
if (pcidev[i].pd_busnr != busnr)
|
|
continue;
|
|
pcidev[i].pd_inuse= 1;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Look for PCI bridges */
|
|
do_pcibridge(busind);
|
|
|
|
/* Allocate bus numbers for uninitialized bridges */
|
|
complete_bridges();
|
|
|
|
/* Allocate I/O and memory resources for uninitialized devices */
|
|
complete_bars();
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* probe_bus *
|
|
*===========================================================================*/
|
|
PRIVATE void probe_bus(busind)
|
|
int busind;
|
|
{
|
|
u32_t dev, func;
|
|
u16_t vid, did, sts;
|
|
u8_t headt;
|
|
u8_t baseclass, subclass, infclass;
|
|
int devind, busnr;
|
|
char *s, *dstr;
|
|
|
|
#if DEBUG
|
|
printf("probe_bus(%d)\n", busind);
|
|
#endif
|
|
if (nr_pcidev >= NR_PCIDEV)
|
|
panic("PCI","too many PCI devices", nr_pcidev);
|
|
devind= nr_pcidev;
|
|
|
|
busnr= pcibus[busind].pb_busnr;
|
|
for (dev= 0; dev<32; dev++)
|
|
{
|
|
|
|
for (func= 0; func < 8; func++)
|
|
{
|
|
pcidev[devind].pd_busnr= busnr;
|
|
pcidev[devind].pd_dev= dev;
|
|
pcidev[devind].pd_func= func;
|
|
|
|
pci_attr_wsts(devind,
|
|
PSR_SSE|PSR_RMAS|PSR_RTAS);
|
|
vid= pci_attr_r16(devind, PCI_VID);
|
|
did= pci_attr_r16(devind, PCI_DID);
|
|
headt= pci_attr_r8(devind, PCI_HEADT);
|
|
sts= pci_attr_rsts(devind);
|
|
|
|
#if 0
|
|
printf("vid 0x%x, did 0x%x, headt 0x%x, sts 0x%x\n",
|
|
vid, did, headt, sts);
|
|
#endif
|
|
|
|
if (vid == NO_VID)
|
|
{
|
|
if (func == 0)
|
|
break; /* Nothing here */
|
|
|
|
/* Scan all functions of a multifunction
|
|
* device.
|
|
*/
|
|
continue;
|
|
}
|
|
|
|
if (sts & (PSR_SSE|PSR_RMAS|PSR_RTAS))
|
|
{
|
|
if (qemu_pci)
|
|
{
|
|
printf(
|
|
"pci: ignoring bad value 0x%x in sts for QEMU\n",
|
|
sts & (PSR_SSE|PSR_RMAS|PSR_RTAS));
|
|
}
|
|
else
|
|
{
|
|
if (func == 0)
|
|
break; /* Nothing here */
|
|
|
|
/* Scan all functions of a
|
|
* multifunction device.
|
|
*/
|
|
continue;
|
|
}
|
|
}
|
|
|
|
dstr= pci_dev_name(vid, did);
|
|
if (debug)
|
|
{
|
|
if (dstr)
|
|
{
|
|
printf("%d.%lu.%lu: %s (%04X/%04X)\n",
|
|
busind, (unsigned long)dev,
|
|
(unsigned long)func, dstr,
|
|
vid, did);
|
|
}
|
|
else
|
|
{
|
|
printf(
|
|
"%d.%lu.%lu: Unknown device, vendor %04X (%s), device %04X\n",
|
|
busind, (unsigned long)dev,
|
|
(unsigned long)func, vid,
|
|
pci_vid_name(vid), did);
|
|
}
|
|
printf("Device index: %d\n", devind);
|
|
printf("Subsystem: Vid 0x%x, did 0x%x\n",
|
|
pci_attr_r16(devind, PCI_SUBVID),
|
|
pci_attr_r16(devind, PCI_SUBDID));
|
|
}
|
|
|
|
baseclass= pci_attr_r8(devind, PCI_BCR);
|
|
subclass= pci_attr_r8(devind, PCI_SCR);
|
|
infclass= pci_attr_r8(devind, PCI_PIFR);
|
|
s= pci_subclass_name(baseclass, subclass, infclass);
|
|
if (!s)
|
|
s= pci_baseclass_name(baseclass);
|
|
{
|
|
if (!s)
|
|
s= "(unknown class)";
|
|
}
|
|
if (debug)
|
|
{
|
|
printf("\tclass %s (%X/%X/%X)\n", s,
|
|
baseclass, subclass, infclass);
|
|
}
|
|
|
|
if (is_duplicate(busnr, dev, func))
|
|
{
|
|
printf("\tduplicate!\n");
|
|
if (func == 0 && !(headt & PHT_MULTIFUNC))
|
|
break;
|
|
continue;
|
|
}
|
|
|
|
devind= nr_pcidev;
|
|
nr_pcidev++;
|
|
pcidev[devind].pd_baseclass= baseclass;
|
|
pcidev[devind].pd_subclass= subclass;
|
|
pcidev[devind].pd_infclass= infclass;
|
|
pcidev[devind].pd_vid= vid;
|
|
pcidev[devind].pd_did= did;
|
|
pcidev[devind].pd_inuse= 0;
|
|
pcidev[devind].pd_bar_nr= 0;
|
|
record_irq(devind);
|
|
switch(headt & PHT_MASK)
|
|
{
|
|
case PHT_NORMAL:
|
|
record_bars(devind);
|
|
break;
|
|
case PHT_BRIDGE:
|
|
record_bars_bridge(devind);
|
|
break;
|
|
case PHT_CARDBUS:
|
|
record_bars_cardbus(devind);
|
|
break;
|
|
default:
|
|
printf("\t%d.%d.%d: unknown header type %d\n",
|
|
busind, dev, func,
|
|
headt & PHT_MASK);
|
|
break;
|
|
}
|
|
|
|
if (debug)
|
|
print_capabilities(devind);
|
|
|
|
if (nr_pcidev >= NR_PCIDEV)
|
|
panic("PCI","too many PCI devices", nr_pcidev);
|
|
devind= nr_pcidev;
|
|
|
|
if (func == 0 && !(headt & PHT_MULTIFUNC))
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* is_duplicate *
|
|
*===========================================================================*/
|
|
PRIVATE int is_duplicate(busnr, dev, func)
|
|
u8_t busnr;
|
|
u8_t dev;
|
|
u8_t func;
|
|
{
|
|
int i;
|
|
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
if (pcidev[i].pd_busnr == busnr &&
|
|
pcidev[i].pd_dev == dev &&
|
|
pcidev[i].pd_func == func)
|
|
{
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* record_irq *
|
|
*===========================================================================*/
|
|
PRIVATE void record_irq(devind)
|
|
int devind;
|
|
{
|
|
int ilr, ipr, busnr, busind, cb_devind;
|
|
|
|
ilr= pci_attr_r8(devind, PCI_ILR);
|
|
ipr= pci_attr_r8(devind, PCI_IPR);
|
|
if (ilr == 0)
|
|
{
|
|
static int first= 1;
|
|
if (ipr && first && debug)
|
|
{
|
|
first= 0;
|
|
printf("PCI: strange, BIOS assigned IRQ0\n");
|
|
}
|
|
ilr= PCI_ILR_UNKNOWN;
|
|
}
|
|
pcidev[devind].pd_ilr= ilr;
|
|
if (ilr == PCI_ILR_UNKNOWN && !ipr)
|
|
{
|
|
}
|
|
else if (ilr != PCI_ILR_UNKNOWN && ipr)
|
|
{
|
|
if (debug)
|
|
printf("\tIRQ %d for INT%c\n", ilr, 'A' + ipr-1);
|
|
}
|
|
else if (ilr != PCI_ILR_UNKNOWN)
|
|
{
|
|
printf(
|
|
"PCI: IRQ %d is assigned, but device %d.%d.%d does not need it\n",
|
|
ilr, pcidev[devind].pd_busnr, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func);
|
|
}
|
|
else
|
|
{
|
|
/* Check for cardbus devices */
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
if (pcibus[busind].pb_type == PBT_CARDBUS)
|
|
{
|
|
cb_devind= pcibus[busind].pb_devind;
|
|
ilr= pcidev[cb_devind].pd_ilr;
|
|
if (ilr != PCI_ILR_UNKNOWN)
|
|
{
|
|
if (debug)
|
|
{
|
|
printf(
|
|
"assigning IRQ %d to Cardbus device\n",
|
|
ilr);
|
|
}
|
|
pci_attr_w8(devind, PCI_ILR, ilr);
|
|
pcidev[devind].pd_ilr= ilr;
|
|
return;
|
|
}
|
|
}
|
|
if(debug) {
|
|
printf(
|
|
"PCI: device %d.%d.%d uses INT%c but is not assigned any IRQ\n",
|
|
pcidev[devind].pd_busnr, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func, 'A' + ipr-1);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* record_bars *
|
|
*===========================================================================*/
|
|
PRIVATE void record_bars(devind)
|
|
int devind;
|
|
{
|
|
int i, reg, prefetch, type;
|
|
u32_t bar, bar2;
|
|
|
|
for (i= 0, reg= PCI_BAR; reg <= PCI_BAR_6; i++, reg += 4)
|
|
{
|
|
record_bar(devind, i);
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* record_bars_bridge *
|
|
*===========================================================================*/
|
|
PRIVATE void record_bars_bridge(devind)
|
|
int devind;
|
|
{
|
|
u32_t base, limit, size;
|
|
|
|
record_bar(devind, 0);
|
|
record_bar(devind, 1);
|
|
|
|
base= ((pci_attr_r8(devind, PPB_IOBASE) & PPB_IOB_MASK) << 8) |
|
|
(pci_attr_r16(devind, PPB_IOBASEU16) << 16);
|
|
limit= 0xff |
|
|
((pci_attr_r8(devind, PPB_IOLIMIT) & PPB_IOL_MASK) << 8) |
|
|
((~PPB_IOL_MASK & 0xff) << 8) |
|
|
(pci_attr_r16(devind, PPB_IOLIMITU16) << 16);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tI/O window: base 0x%x, limit 0x%x, size %d\n",
|
|
base, limit, size);
|
|
}
|
|
|
|
base= ((pci_attr_r16(devind, PPB_MEMBASE) & PPB_MEMB_MASK) << 16);
|
|
limit= 0xffff |
|
|
((pci_attr_r16(devind, PPB_MEMLIMIT) & PPB_MEML_MASK) << 16) |
|
|
((~PPB_MEML_MASK & 0xffff) << 16);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tMemory window: base 0x%x, limit 0x%x, size 0x%x\n",
|
|
base, limit, size);
|
|
}
|
|
|
|
/* Ignore the upper 32 bits */
|
|
base= ((pci_attr_r16(devind, PPB_PFMEMBASE) & PPB_PFMEMB_MASK) << 16);
|
|
limit= 0xffff |
|
|
((pci_attr_r16(devind, PPB_PFMEMLIMIT) &
|
|
PPB_PFMEML_MASK) << 16) |
|
|
((~PPB_PFMEML_MASK & 0xffff) << 16);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf(
|
|
"\tPrefetchable memory window: base 0x%x, limit 0x%x, size 0x%x\n",
|
|
base, limit, size);
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* record_bars_cardbus *
|
|
*===========================================================================*/
|
|
PRIVATE void record_bars_cardbus(devind)
|
|
int devind;
|
|
{
|
|
u32_t base, limit, size;
|
|
|
|
record_bar(devind, 0);
|
|
|
|
base= pci_attr_r32(devind, CBB_MEMBASE_0);
|
|
limit= pci_attr_r32(devind, CBB_MEMLIMIT_0) |
|
|
(~CBB_MEML_MASK & 0xffffffff);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tMemory window 0: base 0x%x, limit 0x%x, size %d\n",
|
|
base, limit, size);
|
|
}
|
|
|
|
base= pci_attr_r32(devind, CBB_MEMBASE_1);
|
|
limit= pci_attr_r32(devind, CBB_MEMLIMIT_1) |
|
|
(~CBB_MEML_MASK & 0xffffffff);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tMemory window 1: base 0x%x, limit 0x%x, size %d\n",
|
|
base, limit, size);
|
|
}
|
|
|
|
base= pci_attr_r32(devind, CBB_IOBASE_0);
|
|
limit= pci_attr_r32(devind, CBB_IOLIMIT_0) |
|
|
(~CBB_IOL_MASK & 0xffffffff);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tI/O window 0: base 0x%x, limit 0x%x, size %d\n",
|
|
base, limit, size);
|
|
}
|
|
|
|
base= pci_attr_r32(devind, CBB_IOBASE_1);
|
|
limit= pci_attr_r32(devind, CBB_IOLIMIT_1) |
|
|
(~CBB_IOL_MASK & 0xffffffff);
|
|
size= limit-base + 1;
|
|
if (debug)
|
|
{
|
|
printf("\tI/O window 1: base 0x%x, limit 0x%x, size %d\n",
|
|
base, limit, size);
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* record_bar *
|
|
*===========================================================================*/
|
|
PRIVATE void record_bar(devind, bar_nr)
|
|
int devind;
|
|
int bar_nr;
|
|
{
|
|
int reg, prefetch, type, dev_bar_nr;
|
|
u32_t bar, bar2;
|
|
|
|
reg= PCI_BAR+4*bar_nr;
|
|
|
|
bar= pci_attr_r32(devind, reg);
|
|
if (bar & PCI_BAR_IO)
|
|
{
|
|
/* Size register */
|
|
pci_attr_w32(devind, reg, 0xffffffff);
|
|
bar2= pci_attr_r32(devind, reg);
|
|
pci_attr_w32(devind, reg, bar);
|
|
|
|
bar &= ~(u32_t)3; /* Clear non-address bits */
|
|
bar2 &= ~(u32_t)3;
|
|
bar2= (~bar2 & 0xffff)+1;
|
|
if (debug)
|
|
{
|
|
printf("\tbar_%d: %d bytes at 0x%x I/O\n",
|
|
bar_nr, bar2, bar);
|
|
}
|
|
|
|
dev_bar_nr= pcidev[devind].pd_bar_nr++;
|
|
assert(dev_bar_nr < BAR_NR);
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_flags= PBF_IO;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_nr= bar_nr;
|
|
if (bar == 0)
|
|
{
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_flags |=
|
|
PBF_INCOMPLETE;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Size register */
|
|
pci_attr_w32(devind, reg, 0xffffffff);
|
|
bar2= pci_attr_r32(devind, reg);
|
|
pci_attr_w32(devind, reg, bar);
|
|
|
|
if (bar2 == 0)
|
|
return; /* Reg. is not implemented */
|
|
|
|
prefetch= !!(bar & PCI_BAR_PREFETCH);
|
|
type= (bar & PCI_BAR_TYPE);
|
|
bar &= ~(u32_t)0xf; /* Clear non-address bits */
|
|
bar2 &= ~(u32_t)0xf;
|
|
bar2= (~bar2)+1;
|
|
if (debug)
|
|
{
|
|
printf("\tbar_%d: 0x%x bytes at 0x%x%s memory\n",
|
|
bar_nr, bar2, bar,
|
|
prefetch ? " prefetchable" : "");
|
|
if (type != 0)
|
|
printf("type = 0x%x\n", type);
|
|
}
|
|
|
|
dev_bar_nr= pcidev[devind].pd_bar_nr++;
|
|
assert(dev_bar_nr < BAR_NR);
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_flags= 0;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2;
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_nr= bar_nr;
|
|
if (bar == 0)
|
|
{
|
|
pcidev[devind].pd_bar[dev_bar_nr].pb_flags |=
|
|
PBF_INCOMPLETE;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* complete_bridges *
|
|
*===========================================================================*/
|
|
PRIVATE void complete_bridges()
|
|
{
|
|
int i, freebus, devind, prim_busnr;
|
|
|
|
for (i= 0; i<nr_pcibus; i++)
|
|
{
|
|
if (!pcibus[i].pb_needinit)
|
|
continue;
|
|
printf("should allocate bus number for bus %d\n", i);
|
|
freebus= get_freebus();
|
|
printf("got bus number %d\n", freebus);
|
|
|
|
devind= pcibus[i].pb_devind;
|
|
|
|
prim_busnr= pcidev[devind].pd_busnr;
|
|
if (prim_busnr != 0)
|
|
{
|
|
printf(
|
|
"complete_bridge: updating subordinate bus number not implemented\n");
|
|
}
|
|
|
|
pcibus[i].pb_needinit= 0;
|
|
pcibus[i].pb_busnr= freebus;
|
|
|
|
printf("devind = %d\n", devind);
|
|
printf("prim_busnr= %d\n", prim_busnr);
|
|
|
|
pci_attr_w8(devind, PPB_PRIMBN, prim_busnr);
|
|
pci_attr_w8(devind, PPB_SECBN, freebus);
|
|
pci_attr_w8(devind, PPB_SUBORDBN, freebus);
|
|
|
|
printf("CR = 0x%x\n", pci_attr_r16(devind, PCI_CR));
|
|
printf("SECBLT = 0x%x\n", pci_attr_r8(devind, PPB_SECBLT));
|
|
printf("BRIDGECTRL = 0x%x\n",
|
|
pci_attr_r16(devind, PPB_BRIDGECTRL));
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* complete_bars *
|
|
*===========================================================================*/
|
|
PRIVATE void complete_bars()
|
|
{
|
|
int i, j, bar_nr, reg;
|
|
u32_t mem_top, io_bottom, io_top, io_high, base, size, v32;
|
|
|
|
mem_top= 0xfe000000; /* Leave space for the CPU (APIC) */
|
|
|
|
/* Find the lowest memory base */
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
for (j= 0; j<pcidev[i].pd_bar_nr; j++)
|
|
{
|
|
if (pcidev[i].pd_bar[j].pb_flags & PBF_IO)
|
|
continue;
|
|
if (pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE)
|
|
continue;
|
|
base= pcidev[i].pd_bar[j].pb_base;
|
|
if (base < mem_top)
|
|
mem_top= base;
|
|
}
|
|
}
|
|
|
|
/* Should check main memory size */
|
|
if (mem_top < 0x80000000)
|
|
panic("pci", "mem_top too low", mem_top);
|
|
|
|
io_top= 0x10000;
|
|
io_bottom= 0x400;
|
|
|
|
/* Find the free I/O space */
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
for (j= 0; j<pcidev[i].pd_bar_nr; j++)
|
|
{
|
|
if (!(pcidev[i].pd_bar[j].pb_flags & PBF_IO))
|
|
continue;
|
|
if (pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE)
|
|
continue;
|
|
base= pcidev[i].pd_bar[j].pb_base;
|
|
size= pcidev[i].pd_bar[j].pb_size;
|
|
if (base >= io_top)
|
|
continue;
|
|
if (base+size <= io_bottom)
|
|
continue;
|
|
if (base+size-io_bottom < io_top-base)
|
|
io_bottom= base+size;
|
|
else
|
|
io_top= base;
|
|
}
|
|
}
|
|
|
|
if (io_top < io_bottom)
|
|
panic("pci", "io_top too low", io_top);
|
|
if (debug)
|
|
printf("I/O range = [0x%x..0x%x>\n", io_bottom, io_top);
|
|
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
for (j= 0; j<pcidev[i].pd_bar_nr; j++)
|
|
{
|
|
if (pcidev[i].pd_bar[j].pb_flags & PBF_IO)
|
|
continue;
|
|
if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE))
|
|
continue;
|
|
size= pcidev[i].pd_bar[j].pb_size;
|
|
if (size < PAGE_SIZE)
|
|
size= PAGE_SIZE;
|
|
base= mem_top-size;
|
|
base &= ~(u32_t)(size-1);
|
|
mem_top= base;
|
|
bar_nr= pcidev[i].pd_bar[j].pb_nr;
|
|
reg= PCI_BAR + 4*bar_nr;
|
|
v32= pci_attr_r32(i, reg);
|
|
pci_attr_w32(i, reg, v32 | base);
|
|
if (debug)
|
|
{
|
|
printf(
|
|
"complete_bars: allocated 0x%x size %d to %d.%d.%d, bar_%d\n",
|
|
base, size, pcidev[i].pd_busnr,
|
|
pcidev[i].pd_dev, pcidev[i].pd_func,
|
|
bar_nr);
|
|
}
|
|
pcidev[i].pd_bar[j].pb_base= base;
|
|
pcidev[i].pd_bar[j].pb_flags &= ~PBF_INCOMPLETE;
|
|
}
|
|
|
|
io_high= io_top;
|
|
for (j= 0; j<pcidev[i].pd_bar_nr; j++)
|
|
{
|
|
if (!(pcidev[i].pd_bar[j].pb_flags & PBF_IO))
|
|
continue;
|
|
if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE))
|
|
continue;
|
|
size= pcidev[i].pd_bar[j].pb_size;
|
|
base= io_top-size;
|
|
base &= ~(u32_t)(size-1);
|
|
|
|
/* Assume that ISA compatibility is required. Only
|
|
* use the lowest 256 bytes out of every 1024 bytes.
|
|
*/
|
|
base &= 0xfcff;
|
|
|
|
if (base < io_bottom)
|
|
panic("pci", "I/O base too low", base);
|
|
|
|
io_top= base;
|
|
bar_nr= pcidev[i].pd_bar[j].pb_nr;
|
|
reg= PCI_BAR + 4*bar_nr;
|
|
v32= pci_attr_r32(i, reg);
|
|
pci_attr_w32(i, reg, v32 | base);
|
|
if (debug)
|
|
{
|
|
printf(
|
|
"complete_bars: allocated 0x%x size %d to %d.%d.%d, bar_%d\n",
|
|
base, size, pcidev[i].pd_busnr,
|
|
pcidev[i].pd_dev, pcidev[i].pd_func,
|
|
bar_nr);
|
|
}
|
|
pcidev[i].pd_bar[j].pb_base= base;
|
|
pcidev[i].pd_bar[j].pb_flags &= ~PBF_INCOMPLETE;
|
|
|
|
}
|
|
if (io_top != io_high)
|
|
update_bridge4dev_io(i, io_top, io_high-io_top);
|
|
}
|
|
|
|
for (i= 0; i<nr_pcidev; i++)
|
|
{
|
|
for (j= 0; j<pcidev[i].pd_bar_nr; j++)
|
|
{
|
|
if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE))
|
|
continue;
|
|
printf("should allocate resources for device %d\n", i);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* update_bridge4dev_io *
|
|
*===========================================================================*/
|
|
PRIVATE void update_bridge4dev_io(devind, io_base, io_size)
|
|
int devind;
|
|
u32_t io_base;
|
|
u32_t io_size;
|
|
{
|
|
int busnr, busind, type, br_devind;
|
|
u16_t v16;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
type= pcibus[busind].pb_type;
|
|
if (type == PBT_INTEL_HOST)
|
|
return; /* Nothing to do for host controller */
|
|
if (type == PBT_PCIBRIDGE)
|
|
{
|
|
printf(
|
|
"update_bridge4dev_io: not implemented for PCI bridges\n");
|
|
return;
|
|
}
|
|
if (type != PBT_CARDBUS)
|
|
panic("pci", "update_bridge4dev_io: strange bus type", type);
|
|
|
|
if (debug)
|
|
{
|
|
printf("update_bridge4dev_io: adding 0x%x at 0x%x\n",
|
|
io_size, io_base);
|
|
}
|
|
br_devind= pcibus[busind].pb_devind;
|
|
pci_attr_w32(br_devind, CBB_IOLIMIT_0, io_base+io_size-1);
|
|
pci_attr_w32(br_devind, CBB_IOBASE_0, io_base);
|
|
|
|
/* Enable I/O access. Enable busmaster access as well. */
|
|
v16= pci_attr_r16(devind, PCI_CR);
|
|
pci_attr_w16(devind, PCI_CR, v16 | PCI_CR_IO_EN | PCI_CR_MAST_EN);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* get_freebus *
|
|
*===========================================================================*/
|
|
PRIVATE int get_freebus()
|
|
{
|
|
int i, freebus;
|
|
|
|
freebus= 1;
|
|
for (i= 0; i<nr_pcibus; i++)
|
|
{
|
|
if (pcibus[i].pb_needinit)
|
|
continue;
|
|
if (pcibus[i].pb_type == PBT_INTEL_HOST)
|
|
continue;
|
|
if (pcibus[i].pb_busnr <= freebus)
|
|
freebus= pcibus[i].pb_busnr+1;
|
|
printf("get_freebus: should check suboridinate bus number\n");
|
|
}
|
|
return freebus;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_isabridge *
|
|
*===========================================================================*/
|
|
PRIVATE int do_isabridge(busind)
|
|
int busind;
|
|
{
|
|
int i, j, r, type, busnr, unknown_bridge, bridge_dev;
|
|
u16_t vid, did;
|
|
char *dstr;
|
|
|
|
unknown_bridge= -1;
|
|
bridge_dev= -1;
|
|
j= 0; /* lint */
|
|
vid= did= 0; /* lint */
|
|
busnr= pcibus[busind].pb_busnr;
|
|
for (i= 0; i< nr_pcidev; i++)
|
|
{
|
|
if (pcidev[i].pd_busnr != busnr)
|
|
continue;
|
|
if (pcidev[i].pd_baseclass == 0x06 &&
|
|
pcidev[i].pd_subclass == 0x01 &&
|
|
pcidev[i].pd_infclass == 0x00)
|
|
{
|
|
/* ISA bridge. Report if no supported bridge is
|
|
* found.
|
|
*/
|
|
unknown_bridge= i;
|
|
}
|
|
|
|
vid= pcidev[i].pd_vid;
|
|
did= pcidev[i].pd_did;
|
|
for (j= 0; pci_isabridge[j].vid != 0; j++)
|
|
{
|
|
if (pci_isabridge[j].vid != vid)
|
|
continue;
|
|
if (pci_isabridge[j].did != did)
|
|
continue;
|
|
if (pci_isabridge[j].checkclass &&
|
|
unknown_bridge != i)
|
|
{
|
|
/* This part of multifunction device is
|
|
* not the bridge.
|
|
*/
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
if (pci_isabridge[j].vid)
|
|
{
|
|
bridge_dev= i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (bridge_dev != -1)
|
|
{
|
|
dstr= pci_dev_name(vid, did);
|
|
if (!dstr)
|
|
dstr= "unknown device";
|
|
if (debug)
|
|
{
|
|
printf("found ISA bridge (%04X/%04X) %s\n",
|
|
vid, did, dstr);
|
|
}
|
|
pcibus[busind].pb_isabridge_dev= bridge_dev;
|
|
type= pci_isabridge[j].type;
|
|
pcibus[busind].pb_isabridge_type= type;
|
|
switch(type)
|
|
{
|
|
case PCI_IB_PIIX:
|
|
r= do_piix(bridge_dev);
|
|
break;
|
|
case PCI_IB_VIA:
|
|
r= do_via_isabr(bridge_dev);
|
|
break;
|
|
case PCI_IB_AMD:
|
|
r= do_amd_isabr(bridge_dev);
|
|
break;
|
|
case PCI_IB_SIS:
|
|
r= do_sis_isabr(bridge_dev);
|
|
break;
|
|
default:
|
|
panic("PCI","unknown ISA bridge type", type);
|
|
}
|
|
return r;
|
|
}
|
|
|
|
if (unknown_bridge == -1)
|
|
{
|
|
if (debug)
|
|
{
|
|
printf("(warning) no ISA bridge found on bus %d\n",
|
|
busind);
|
|
}
|
|
return 0;
|
|
}
|
|
printf("(warning) unsupported ISA bridge %04X/%04X for bus %d\n",
|
|
pcidev[unknown_bridge].pd_vid,
|
|
pcidev[unknown_bridge].pd_did,
|
|
busind);
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_pcibridge *
|
|
*===========================================================================*/
|
|
PRIVATE void do_pcibridge(busind)
|
|
int busind;
|
|
{
|
|
int i, devind, busnr;
|
|
int ind, type;
|
|
u16_t vid, did;
|
|
u8_t sbusn, baseclass, subclass, infclass, headt;
|
|
u32_t t3;
|
|
|
|
vid= did= 0; /* lint */
|
|
busnr= pcibus[busind].pb_busnr;
|
|
for (devind= 0; devind< nr_pcidev; devind++)
|
|
{
|
|
#if 0
|
|
printf("do_pcibridge: trying %u.%u.%u\n",
|
|
pcidev[devind].pd_busind, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func);
|
|
#endif
|
|
|
|
if (pcidev[devind].pd_busnr != busnr)
|
|
{
|
|
#if 0
|
|
printf("wrong bus\n");
|
|
#endif
|
|
continue;
|
|
}
|
|
|
|
vid= pcidev[devind].pd_vid;
|
|
did= pcidev[devind].pd_did;
|
|
for (i= 0; pci_pcibridge[i].vid != 0; i++)
|
|
{
|
|
if (pci_pcibridge[i].vid != vid)
|
|
continue;
|
|
if (pci_pcibridge[i].did != did)
|
|
continue;
|
|
break;
|
|
}
|
|
type= pci_pcibridge[i].type;
|
|
if (pci_pcibridge[i].vid == 0)
|
|
{
|
|
headt= pci_attr_r8(devind, PCI_HEADT);
|
|
type= 0;
|
|
if ((headt & PHT_MASK) == PHT_BRIDGE)
|
|
type= PCI_PPB_STD;
|
|
else if ((headt & PHT_MASK) == PHT_CARDBUS)
|
|
type= PCI_PPB_CB;
|
|
else
|
|
{
|
|
#if 0
|
|
printf("not a bridge\n");
|
|
#endif
|
|
continue; /* Not a bridge */
|
|
}
|
|
|
|
baseclass= pci_attr_r8(devind, PCI_BCR);
|
|
subclass= pci_attr_r8(devind, PCI_SCR);
|
|
infclass= pci_attr_r8(devind, PCI_PIFR);
|
|
t3= ((baseclass << 16) | (subclass << 8) | infclass);
|
|
if (type == PCI_PPB_STD &&
|
|
t3 != PCI_T3_PCI2PCI &&
|
|
t3 != PCI_T3_PCI2PCI_SUBTR)
|
|
{
|
|
printf(
|
|
"Unknown PCI class %02x:%02x:%02x for PCI-to-PCI bridge, device %04X/%04X\n",
|
|
baseclass, subclass, infclass,
|
|
vid, did);
|
|
continue;
|
|
}
|
|
if (type == PCI_PPB_CB &&
|
|
t3 != PCI_T3_CARDBUS)
|
|
{
|
|
printf(
|
|
"Unknown PCI class %02x:%02x:%02x for Cardbus bridge, device %04X/%04X\n",
|
|
baseclass, subclass, infclass,
|
|
vid, did);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if (debug)
|
|
{
|
|
printf("%u.%u.%u: PCI-to-PCI bridge: %04X/%04X\n",
|
|
pcidev[devind].pd_busnr,
|
|
pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func, vid, did);
|
|
}
|
|
|
|
/* Assume that the BIOS initialized the secondary bus
|
|
* number.
|
|
*/
|
|
sbusn= pci_attr_r8(devind, PPB_SECBN);
|
|
#if DEBUG
|
|
printf("sbusn = %d\n", sbusn);
|
|
printf("subordn = %d\n", pci_attr_r8(devind, PPB_SUBORDBN));
|
|
#endif
|
|
|
|
if (nr_pcibus >= NR_PCIBUS)
|
|
panic("PCI","too many PCI busses", nr_pcibus);
|
|
ind= nr_pcibus;
|
|
nr_pcibus++;
|
|
pcibus[ind].pb_type= PBT_PCIBRIDGE;
|
|
pcibus[ind].pb_needinit= 1;
|
|
pcibus[ind].pb_isabridge_dev= -1;
|
|
pcibus[ind].pb_isabridge_type= 0;
|
|
pcibus[ind].pb_devind= devind;
|
|
pcibus[ind].pb_busnr= sbusn;
|
|
pcibus[ind].pb_rreg8= pcibus[busind].pb_rreg8;
|
|
pcibus[ind].pb_rreg16= pcibus[busind].pb_rreg16;
|
|
pcibus[ind].pb_rreg32= pcibus[busind].pb_rreg32;
|
|
pcibus[ind].pb_wreg8= pcibus[busind].pb_wreg8;
|
|
pcibus[ind].pb_wreg16= pcibus[busind].pb_wreg16;
|
|
pcibus[ind].pb_wreg32= pcibus[busind].pb_wreg32;
|
|
switch(type)
|
|
{
|
|
case PCI_PPB_STD:
|
|
pcibus[ind].pb_rsts= pcibr_std_rsts;
|
|
pcibus[ind].pb_wsts= pcibr_std_wsts;
|
|
break;
|
|
case PCI_PPB_CB:
|
|
pcibus[ind].pb_type= PBT_CARDBUS;
|
|
pcibus[ind].pb_rsts= pcibr_cb_rsts;
|
|
pcibus[ind].pb_wsts= pcibr_cb_wsts;
|
|
break;
|
|
case PCI_AGPB_VIA:
|
|
pcibus[ind].pb_rsts= pcibr_via_rsts;
|
|
pcibus[ind].pb_wsts= pcibr_via_wsts;
|
|
break;
|
|
default:
|
|
panic("PCI","unknown PCI-PCI bridge type", type);
|
|
}
|
|
if (sbusn == 0)
|
|
{
|
|
printf("Secondary bus number not initialized\n");
|
|
continue;
|
|
}
|
|
pcibus[ind].pb_needinit= 0;
|
|
|
|
probe_bus(ind);
|
|
|
|
/* Look for PCI bridges */
|
|
do_pcibridge(ind);
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* get_busind *
|
|
*===========================================================================*/
|
|
PRIVATE int get_busind(busnr)
|
|
int busnr;
|
|
{
|
|
int i;
|
|
|
|
for (i= 0; i<nr_pcibus; i++)
|
|
{
|
|
if (pcibus[i].pb_busnr == busnr)
|
|
return i;
|
|
}
|
|
panic("pci", "get_busind: can't find bus", busnr);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_piix *
|
|
*===========================================================================*/
|
|
PRIVATE int do_piix(devind)
|
|
int devind;
|
|
{
|
|
int i, s, dev, func, irqrc, irq;
|
|
u32_t elcr1, elcr2, elcr;
|
|
|
|
#if DEBUG
|
|
printf("in piix\n");
|
|
#endif
|
|
dev= pcidev[devind].pd_dev;
|
|
func= pcidev[devind].pd_func;
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_inb(PIIX_ELCR1, &elcr1)))
|
|
printf("Warning, sys_inb failed: %d\n", s);
|
|
if (OK != (s=sys_inb(PIIX_ELCR2, &elcr2)))
|
|
printf("Warning, sys_inb failed: %d\n", s);
|
|
#else
|
|
elcr1= inb(PIIX_ELCR1);
|
|
elcr2= inb(PIIX_ELCR2);
|
|
#endif
|
|
elcr= elcr1 | (elcr2 << 8);
|
|
for (i= 0; i<4; i++)
|
|
{
|
|
irqrc= pci_attr_r8(devind, PIIX_PIRQRCA+i);
|
|
if (irqrc & PIIX_IRQ_DI)
|
|
{
|
|
if (debug)
|
|
printf("INT%c: disabled\n", 'A'+i);
|
|
}
|
|
else
|
|
{
|
|
irq= irqrc & PIIX_IRQ_MASK;
|
|
if (debug)
|
|
printf("INT%c: %d\n", 'A'+i, irq);
|
|
if (!(elcr & (1 << irq)))
|
|
{
|
|
if (debug)
|
|
{
|
|
printf(
|
|
"(warning) IRQ %d is not level triggered\n",
|
|
irq);
|
|
}
|
|
}
|
|
irq_mode_pci(irq);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_amd_isabr *
|
|
*===========================================================================*/
|
|
PRIVATE int do_amd_isabr(devind)
|
|
int devind;
|
|
{
|
|
int i, busnr, dev, func, xdevind, irq, edge;
|
|
u8_t levmask;
|
|
u16_t pciirq;
|
|
|
|
/* Find required function */
|
|
func= AMD_ISABR_FUNC;
|
|
busnr= pcidev[devind].pd_busnr;
|
|
dev= pcidev[devind].pd_dev;
|
|
|
|
/* Fake a device with the required function */
|
|
if (nr_pcidev >= NR_PCIDEV)
|
|
panic("PCI","too many PCI devices", nr_pcidev);
|
|
xdevind= nr_pcidev;
|
|
pcidev[xdevind].pd_busnr= busnr;
|
|
pcidev[xdevind].pd_dev= dev;
|
|
pcidev[xdevind].pd_func= func;
|
|
pcidev[xdevind].pd_inuse= 1;
|
|
nr_pcidev++;
|
|
|
|
levmask= pci_attr_r8(xdevind, AMD_ISABR_PCIIRQ_LEV);
|
|
pciirq= pci_attr_r16(xdevind, AMD_ISABR_PCIIRQ_ROUTE);
|
|
for (i= 0; i<4; i++)
|
|
{
|
|
edge= (levmask >> i) & 1;
|
|
irq= (pciirq >> (4*i)) & 0xf;
|
|
if (!irq)
|
|
{
|
|
if (debug)
|
|
printf("INT%c: disabled\n", 'A'+i);
|
|
}
|
|
else
|
|
{
|
|
if (debug)
|
|
printf("INT%c: %d\n", 'A'+i, irq);
|
|
if (edge && debug)
|
|
{
|
|
printf(
|
|
"(warning) IRQ %d is not level triggered\n",
|
|
irq);
|
|
}
|
|
irq_mode_pci(irq);
|
|
}
|
|
}
|
|
nr_pcidev--;
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_sis_isabr *
|
|
*===========================================================================*/
|
|
PRIVATE int do_sis_isabr(devind)
|
|
int devind;
|
|
{
|
|
int i, dev, func, irq;
|
|
|
|
dev= pcidev[devind].pd_dev;
|
|
func= pcidev[devind].pd_func;
|
|
irq= 0; /* lint */
|
|
for (i= 0; i<4; i++)
|
|
{
|
|
irq= pci_attr_r8(devind, SIS_ISABR_IRQ_A+i);
|
|
if (irq & SIS_IRQ_DISABLED)
|
|
{
|
|
if (debug)
|
|
printf("INT%c: disabled\n", 'A'+i);
|
|
}
|
|
else
|
|
{
|
|
irq &= SIS_IRQ_MASK;
|
|
if (debug)
|
|
printf("INT%c: %d\n", 'A'+i, irq);
|
|
irq_mode_pci(irq);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_via_isabr *
|
|
*===========================================================================*/
|
|
PRIVATE int do_via_isabr(devind)
|
|
int devind;
|
|
{
|
|
int i, dev, func, irq, edge;
|
|
u8_t levmask;
|
|
|
|
dev= pcidev[devind].pd_dev;
|
|
func= pcidev[devind].pd_func;
|
|
levmask= pci_attr_r8(devind, VIA_ISABR_EL);
|
|
irq= 0; /* lint */
|
|
edge= 0; /* lint */
|
|
for (i= 0; i<4; i++)
|
|
{
|
|
switch(i)
|
|
{
|
|
case 0:
|
|
edge= (levmask & VIA_ISABR_EL_INTA);
|
|
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R2) >> 4;
|
|
break;
|
|
case 1:
|
|
edge= (levmask & VIA_ISABR_EL_INTB);
|
|
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R2);
|
|
break;
|
|
case 2:
|
|
edge= (levmask & VIA_ISABR_EL_INTC);
|
|
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R3) >> 4;
|
|
break;
|
|
case 3:
|
|
edge= (levmask & VIA_ISABR_EL_INTD);
|
|
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R1) >> 4;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
}
|
|
irq &= 0xf;
|
|
if (!irq)
|
|
{
|
|
if (debug)
|
|
printf("INT%c: disabled\n", 'A'+i);
|
|
}
|
|
else
|
|
{
|
|
if (debug)
|
|
printf("INT%c: %d\n", 'A'+i, irq);
|
|
if (edge && debug)
|
|
{
|
|
printf(
|
|
"(warning) IRQ %d is not level triggered\n",
|
|
irq);
|
|
}
|
|
irq_mode_pci(irq);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_vid_name *
|
|
*===========================================================================*/
|
|
PRIVATE char *pci_vid_name(vid)
|
|
u16_t vid;
|
|
{
|
|
int i;
|
|
|
|
for (i= 0; pci_vendor_table[i].name; i++)
|
|
{
|
|
if (pci_vendor_table[i].vid == vid)
|
|
return pci_vendor_table[i].name;
|
|
}
|
|
return "unknown";
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_baseclass_name *
|
|
*===========================================================================*/
|
|
PRIVATE char *pci_baseclass_name(baseclass)
|
|
u8_t baseclass;
|
|
{
|
|
int i;
|
|
|
|
for (i= 0; pci_baseclass_table[i].name; i++)
|
|
{
|
|
if (pci_baseclass_table[i].baseclass == baseclass)
|
|
return pci_baseclass_table[i].name;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_subclass_name *
|
|
*===========================================================================*/
|
|
PRIVATE char *pci_subclass_name(baseclass, subclass, infclass)
|
|
u8_t baseclass;
|
|
u8_t subclass;
|
|
u8_t infclass;
|
|
{
|
|
int i;
|
|
|
|
for (i= 0; pci_subclass_table[i].name; i++)
|
|
{
|
|
if (pci_subclass_table[i].baseclass != baseclass)
|
|
continue;
|
|
if (pci_subclass_table[i].subclass != subclass)
|
|
continue;
|
|
if (pci_subclass_table[i].infclass != infclass &&
|
|
pci_subclass_table[i].infclass != (u16_t)-1)
|
|
{
|
|
continue;
|
|
}
|
|
return pci_subclass_table[i].name;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* ntostr *
|
|
*===========================================================================*/
|
|
PRIVATE void ntostr(n, str, end)
|
|
unsigned n;
|
|
char **str;
|
|
char *end;
|
|
{
|
|
char tmpstr[20];
|
|
int i;
|
|
|
|
if (n == 0)
|
|
{
|
|
tmpstr[0]= '0';
|
|
i= 1;
|
|
}
|
|
else
|
|
{
|
|
for (i= 0; n; i++)
|
|
{
|
|
tmpstr[i]= '0' + (n%10);
|
|
n /= 10;
|
|
}
|
|
}
|
|
for (; i>0; i--)
|
|
{
|
|
if (*str == end)
|
|
{
|
|
break;
|
|
}
|
|
**str= tmpstr[i-1];
|
|
(*str)++;
|
|
}
|
|
if (*str == end)
|
|
end[-1]= '\0';
|
|
else
|
|
**str= '\0';
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_attr_rsts *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pci_attr_rsts(devind)
|
|
int devind;
|
|
{
|
|
int busnr, busind;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
return pcibus[busind].pb_rsts(busind);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* pcibr_std_rsts *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pcibr_std_rsts(busind)
|
|
int busind;
|
|
{
|
|
int devind;
|
|
|
|
devind= pcibus[busind].pb_devind;
|
|
return pci_attr_r16(devind, PPB_SSTS);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcibr_std_wsts *
|
|
*===========================================================================*/
|
|
PRIVATE void pcibr_std_wsts(busind, value)
|
|
int busind;
|
|
u16_t value;
|
|
{
|
|
int devind;
|
|
devind= pcibus[busind].pb_devind;
|
|
|
|
#if 0
|
|
printf("pcibr_std_wsts(%d, 0x%X), devind= %d\n",
|
|
busind, value, devind);
|
|
#endif
|
|
pci_attr_w16(devind, PPB_SSTS, value);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcibr_cb_rsts *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pcibr_cb_rsts(busind)
|
|
int busind;
|
|
{
|
|
int devind;
|
|
devind= pcibus[busind].pb_devind;
|
|
|
|
return pci_attr_r16(devind, CBB_SSTS);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcibr_cb_wsts *
|
|
*===========================================================================*/
|
|
PRIVATE void pcibr_cb_wsts(busind, value)
|
|
int busind;
|
|
u16_t value;
|
|
{
|
|
int devind;
|
|
devind= pcibus[busind].pb_devind;
|
|
|
|
#if 0
|
|
printf("pcibr_cb_wsts(%d, 0x%X), devind= %d\n",
|
|
busind, value, devind);
|
|
#endif
|
|
pci_attr_w16(devind, CBB_SSTS, value);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcibr_via_rsts *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pcibr_via_rsts(busind)
|
|
int busind;
|
|
{
|
|
int devind;
|
|
devind= pcibus[busind].pb_devind;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcibr_via_wsts *
|
|
*===========================================================================*/
|
|
PRIVATE void pcibr_via_wsts(busind, value)
|
|
int busind;
|
|
u16_t value;
|
|
{
|
|
int devind;
|
|
devind= pcibus[busind].pb_devind;
|
|
|
|
#if 0
|
|
printf("pcibr_via_wsts(%d, 0x%X), devind= %d (not implemented)\n",
|
|
busind, value, devind);
|
|
#endif
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pci_attr_wsts *
|
|
*===========================================================================*/
|
|
PRIVATE void pci_attr_wsts(devind, value)
|
|
int devind;
|
|
u16_t value;
|
|
{
|
|
int busnr, busind;
|
|
|
|
busnr= pcidev[devind].pd_busnr;
|
|
busind= get_busind(busnr);
|
|
pcibus[busind].pb_wsts(busind, value);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* pcii_rreg8 *
|
|
*===========================================================================*/
|
|
PRIVATE u8_t pcii_rreg8(busind, devind, port)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
{
|
|
u8_t v;
|
|
int s;
|
|
|
|
v= PCII_RREG8_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
#if 0
|
|
printf("pcii_rreg8(%d, %d, 0x%X): %d.%d.%d= 0x%X\n",
|
|
busind, devind, port,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func, v);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_rreg16 *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pcii_rreg16(busind, devind, port)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
{
|
|
u16_t v;
|
|
int s;
|
|
|
|
v= PCII_RREG16_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n");
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
#if 0
|
|
printf("pcii_rreg16(%d, %d, 0x%X): %d.%d.%d= 0x%X\n",
|
|
busind, devind, port,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func, v);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_rreg32 *
|
|
*===========================================================================*/
|
|
PRIVATE u32_t pcii_rreg32(busind, devind, port)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
{
|
|
u32_t v;
|
|
int s;
|
|
|
|
v= PCII_RREG32_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
#if 0
|
|
printf("pcii_rreg32(%d, %d, 0x%X): %d.%d.%d= 0x%X\n",
|
|
busind, devind, port,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func, v);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_wreg8 *
|
|
*===========================================================================*/
|
|
PRIVATE void pcii_wreg8(busind, devind, port, value)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
u8_t value;
|
|
{
|
|
int s;
|
|
#if 0
|
|
printf("pcii_wreg8(%d, %d, 0x%X, 0x%X): %d.%d.%d\n",
|
|
busind, devind, port, value,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func);
|
|
#endif
|
|
PCII_WREG8_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port, value);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_wreg16 *
|
|
*===========================================================================*/
|
|
PRIVATE void pcii_wreg16(busind, devind, port, value)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
u16_t value;
|
|
{
|
|
int s;
|
|
#if 0
|
|
printf("pcii_wreg16(%d, %d, 0x%X, 0x%X): %d.%d.%d\n",
|
|
busind, devind, port, value,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func);
|
|
#endif
|
|
PCII_WREG16_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port, value);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_wreg32 *
|
|
*===========================================================================*/
|
|
PRIVATE void pcii_wreg32(busind, devind, port, value)
|
|
int busind;
|
|
int devind;
|
|
int port;
|
|
u32_t value;
|
|
{
|
|
int s;
|
|
#if 0
|
|
printf("pcii_wreg32(%d, %d, 0x%X, 0x%X): %d.%d.%d\n",
|
|
busind, devind, port, value,
|
|
pcibus[busind].pb_bus, pcidev[devind].pd_dev,
|
|
pcidev[devind].pd_func);
|
|
#endif
|
|
PCII_WREG32_(pcibus[busind].pb_busnr,
|
|
pcidev[devind].pd_dev, pcidev[devind].pd_func,
|
|
port, value);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n");
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_rsts *
|
|
*===========================================================================*/
|
|
PRIVATE u16_t pcii_rsts(busind)
|
|
int busind;
|
|
{
|
|
u16_t v;
|
|
int s;
|
|
|
|
v= PCII_RREG16_(pcibus[busind].pb_busnr, 0, 0, PCI_SR);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* pcii_wsts *
|
|
*===========================================================================*/
|
|
PRIVATE void pcii_wsts(busind, value)
|
|
int busind;
|
|
u16_t value;
|
|
{
|
|
int s;
|
|
PCII_WREG16_(pcibus[busind].pb_busnr, 0, 0, PCI_SR, value);
|
|
#if USER_SPACE
|
|
if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL)))
|
|
printf("PCI: warning, sys_outl failed: %d\n", s);
|
|
#else
|
|
outl(PCII_CONFADD, PCII_UNSEL);
|
|
#endif
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* print_capabilities *
|
|
*===========================================================================*/
|
|
PRIVATE void print_capabilities(devind)
|
|
int devind;
|
|
{
|
|
u8_t status, capptr, type, next;
|
|
char *str;
|
|
|
|
/* Check capabilities bit in the device status register */
|
|
status= pci_attr_r16(devind, PCI_SR);
|
|
if (!(status & PSR_CAPPTR))
|
|
return;
|
|
|
|
capptr= (pci_attr_r8(devind, PCI_CAPPTR) & PCI_CP_MASK);
|
|
while (capptr != 0)
|
|
{
|
|
type = pci_attr_r8(devind, capptr+CAP_TYPE);
|
|
next= (pci_attr_r8(devind, capptr+CAP_NEXT) & PCI_CP_MASK);
|
|
switch(type)
|
|
{
|
|
case 1: str= "PCI Power Management"; break;
|
|
case 2: str= "AGP"; break;
|
|
case 3: str= "Vital Product Data"; break;
|
|
case 4: str= "Slot Identification"; break;
|
|
case 5: str= "Message Signaled Interrupts"; break;
|
|
case 6: str= "CompactPCI Hot Swap"; break;
|
|
case 8: str= "AMD HyperTransport"; break;
|
|
case 0xf: str= "AMD I/O MMU"; break;
|
|
defuault: str= "(unknown type)"; break;
|
|
}
|
|
|
|
printf(" @0x%x: capability type 0x%x: %s\n",
|
|
capptr, type, str);
|
|
capptr= next;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* $PchId: pci.c,v 1.7 2003/08/07 09:06:51 philip Exp $
|
|
*/
|