Kees Jongenburger d77debb5b7 arm:caching access the l1 pages over cacheable memory.
When we start using a new pagetable (for a new process)
the last part is to ensure the pagetable itself can be
accessed by VM. This is done in pt_bind by updating
the "pagetable of pagetables" and we want this mapping
to match other mappings to the l1 pagetable.

Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d
2013-09-26 11:57:44 +02:00
..
2012-07-15 22:30:15 +02:00