Kees Jongenburger d77debb5b7 arm:caching access the l1 pages over cacheable memory.
When we start using a new pagetable (for a new process)
the last part is to ensure the pagetable itself can be
accessed by VM. This is done in pt_bind by updating
the "pagetable of pagetables" and we want this mapping
to match other mappings to the l1 pagetable.

Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d
2013-09-26 11:57:44 +02:00
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2013-08-20 11:37:40 +02:00
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2013-09-26 09:05:44 +02:00
2013-08-21 13:53:39 +02:00
2013-09-01 12:59:37 +00:00
2013-09-26 09:05:28 +02:00
2013-09-25 19:30:22 +02:00
2013-08-21 13:53:39 +02:00
2010-01-21 10:16:05 +00:00
Description
A fun microkernel meant to match modern usecases
GPL-3.0 148 MiB
Languages
C 78.2%
Roff 10.2%
Assembly 4.6%
Shell 3.7%
Makefile 1.6%
Other 1.2%