197 lines
8.0 KiB
C
197 lines
8.0 KiB
C
#ifndef __SYS_VM_ARM_H__
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#define __SYS_VM_ARM_H__
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/*
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arm/vm.h
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*/
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/*
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* We are using the following setup
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* the system is configured to have the TRE (Tex remap enable bit) set to 0
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* The TEX[2:0] B and C bits are used to determins memory attributes.
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* These bits together with the S Bit (Shareability Bit) determines the
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* memory attributes.
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*
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* The S bit is ignored when the other attribute define the memory as
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* "device" or "strongly ordered"
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*
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* We are setting the tex[2] bit to one to end up with the following
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* encoding
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*
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* 00 00 Non cacheable
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* 01 01 Write back, Write allocate
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* 10 10 Write trough, No write allocate
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* 11 11 Write back , Write alloc
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*/
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#define ARM_PAGE_SIZE 4096 /* small page on ARM */
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#define ARM_SECTION_SIZE (1024 * 1024) /* 1 MB section */
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/* Second level page table entries */
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#define ARM_VM_PAGETABLE (1 << 1) /* Page table */
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#define ARM_VM_PTE_PRESENT (1 << 1) /* Page is present */
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#define ARM_VM_PTE_B (1 << 2) /* B bit */
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#define ARM_VM_PTE_C (1 << 3) /* C bit */
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#define ARM_VM_PTE_SUPER (0x1 << 4) /* Super access only AP[1:0] */
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#define ARM_VM_PTE_USER (0x3 << 4) /* Super/User access AP[1:0] */
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#define ARM_VM_PTE_TEX0 (1 << 6) /* TEX[0] */
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#define ARM_VM_PTE_TEX1 (1 << 7) /* TEX[1] */
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#define ARM_VM_PTE_TEX2 (1 << 8) /* TEX[2] */
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#define ARM_VM_PTE_RO (1 << 9) /* Read only access AP[2] */
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#define ARM_VM_PTE_RW (0 << 9) /* Read-write access AP[2] */
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#define ARM_VM_PTE_S (1 << 10) /* "Shareable" */
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#define ARM_VM_PTE_NOTGLOBAL (1 << 11) /* Not Global */
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/* inner and outer write-back, write-allocate */
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#define ARM_VM_PTE_WB (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX0 | ARM_VM_PTE_B)
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/* inner and outer write-through, no write-allocate */
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#define ARM_VM_PTE_WT (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX1 | ARM_VM_PTE_C )
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/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
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#define ARM_VM_PTE_WTWB (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX0 | ARM_VM_PTE_C )
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#define ARM_VM_PTE_CACHED ARM_VM_PTE_WTWB
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/* shareable device */
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#define ARM_VM_PTE_DEVICE (ARM_VM_PTE_B)
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#define ARM_VM_ADDR_MASK 0xFFFFF000 /* physical address */
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#define ARM_VM_ADDR_MASK_1MB 0xFFF00000 /* physical address */
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#define ARM_VM_OFFSET_MASK_1MB 0x000FFFFF /* physical address */
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/* Big page (1MB section) specific flags. */
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#define ARM_VM_SECTION (1 << 1) /* 1MB section */
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#define ARM_VM_SECTION_PRESENT (1 << 1) /* Section is present */
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#define ARM_VM_SECTION_B (1 << 2) /* B Bit */
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#define ARM_VM_SECTION_C (1 << 3) /* C Bit */
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#define ARM_VM_SECTION_DOMAIN (0xF << 5) /* Domain Number */
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#define ARM_VM_SECTION_SUPER (0x1 << 10) /* Super access only AP[1:0] */
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#define ARM_VM_SECTION_USER (0x3 << 10) /* Super/User access AP[1:0] */
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#define ARM_VM_SECTION_TEX0 (1 << 12) /* TEX[0] */
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#define ARM_VM_SECTION_TEX1 (1 << 13) /* TEX[1] */
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#define ARM_VM_SECTION_TEX2 (1 << 14) /* TEX[2] */
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#define ARM_VM_SECTION_RO (1 << 15) /* Read only access AP[2] */
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#define ARM_VM_SECTION_SHAREABLE (1 << 16) /* Shareable */
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#define ARM_VM_SECTION_NOTGLOBAL (1 << 17) /* Not Global */
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/* inner and outer write-back, write-allocate */
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#define ARM_VM_SECTION_WB (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
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/* inner and outer write-through, no write-allocate */
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#define ARM_VM_SECTION_WT (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
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/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
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#define ARM_VM_SECTION_WTWB (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
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/* shareable device */
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#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB
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#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B)
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/* Page directory specific flags. */
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#define ARM_VM_PAGEDIR (1 << 0) /* Page directory */
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#define ARM_VM_PDE_PRESENT (1 << 0) /* Page directory is present */
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#define ARM_VM_PDE_DOMAIN (0xF << 5) /* Domain Number */
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#define ARM_VM_PT_ENT_SIZE 4 /* Size of a page table entry */
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#define ARM_VM_DIR_ENT_SIZE 4 /* Size of a page dir entry */
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#define ARM_VM_DIR_ENTRIES 4096 /* Number of entries in a page dir */
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#define ARM_VM_DIR_ENT_SHIFT 20 /* Shift to get entry in page dir. */
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#define ARM_VM_PT_ENT_SHIFT 12 /* Shift to get entry in page table */
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#define ARM_VM_PT_ENT_MASK 0xFF /* Mask to get entry in page table */
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#define ARM_VM_PT_ENTRIES 256 /* Number of entries in a page table */
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#define ARM_VM_PTE(v) (((v) >> ARM_VM_PT_ENT_SHIFT) & ARM_VM_PT_ENT_MASK)
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#define ARM_VM_PDE(v) ( (v) >> ARM_VM_DIR_ENT_SHIFT)
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#define ARM_VM_PFA(e) ( (e) & ARM_VM_ADDR_MASK)
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/* Second level small pages entry(Page Table Entry) points to 4K */
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#define ARM_VM_PTE_SHIFT 12
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#define ARM_VM_PTE_MASK (~((1 << ARM_VM_PTE_SHIFT) - 1))
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/* First level entry(Page Directory Entry) to a second level small page PTE */
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#define ARM_VM_PDE_SHIFT 10
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#define ARM_VM_PDE_MASK (~((1 << ARM_VM_PDE_SHIFT) - 1))
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/* First level entry(Page Directory Entry) to a 1MB section */
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#define ARM_VM_SECTION_SHIFT 20
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#define ARM_VM_SECTION_MASK (~((1 << ARM_VM_SECTION_SHIFT) - 1))
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#define ARM_VM_DIR_SIZE (ARM_VM_DIR_ENTRIES * ARM_VM_DIR_ENT_SIZE)
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#define ARM_PAGEDIR_SIZE (ARM_VM_DIR_SIZE)
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#define ARM_VM_PT_SIZE (ARM_VM_PT_ENTRIES * ARM_VM_PT_ENT_SIZE)
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#define ARM_PAGETABLE_SIZE (ARM_VM_PT_SIZE)
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/* ARM pagefault status bits */
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#define ARM_VM_PFE_ALIGN 0x01 /* Pagefault caused by Alignment fault */
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#define ARM_VM_PFE_IMAINT 0x04 /* Caused by Instruction cache
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maintenance fault */
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#define ARM_VM_PFE_TTWALK_L1ABORT 0x0c /* Caused by Synchronous external abort
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* on translation table walk (Level 1)
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*/
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#define ARM_VM_PFE_TTWALK_L2ABORT 0x0e /* Caused by Synchronous external abort
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* on translation table walk (Level 2)
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*/
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#define ARM_VM_PFE_TTWALK_L1PERR 0x1c /* Caused by Parity error
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* on translation table walk (Level 1)
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*/
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#define ARM_VM_PFE_TTWALK_L2PERR 0x1e /* Caused by Parity error
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* on translation table walk (Level 2)
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*/
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#define ARM_VM_PFE_L1TRANS 0x05 /* Caused by Translation fault (Level 1)
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*/
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#define ARM_VM_PFE_L2TRANS 0x07 /* Caused by Translation fault (Level 2)
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*/
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#define ARM_VM_PFE_L1ACCESS 0x03 /* Caused by Access flag fault (Level 1)
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*/
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#define ARM_VM_PFE_L2ACCESS 0x06 /* Caused by Access flag fault (Level 2)
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*/
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#define ARM_VM_PFE_L1DOMAIN 0x09 /* Caused by Domain fault (Level 1)
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*/
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#define ARM_VM_PFE_L2DOMAIN 0x0b /* Caused by Domain fault (Level 2)
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*/
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#define ARM_VM_PFE_L1PERM 0x0d /* Caused by Permission fault (Level 1)
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*/
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#define ARM_VM_PFE_L2PERM 0x0f /* Caused by Permission fault (Level 2)
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*/
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#define ARM_VM_PFE_DEBUG 0x02 /* Caused by Debug event */
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#define ARM_VM_PFE_ABORT 0x08 /* Caused by Synchronous external abort
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*/
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#define ARM_VM_PFE_TLB_CONFLICT 0x10 /* Caused by TLB conflict abort
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*/
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#define ARM_VM_PFE_W (1<<11) /* Caused by write (otherwise read) */
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#define ARM_VM_PFE_FS4 (1<<10) /* Fault status (bit 4) */
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#define ARM_VM_PFE_FS3_0 0xf /* Fault status (bits 3:0) */
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/* Translation table base register specfic flags */
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#define ARM_TTBR_C (0x01) /* Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory. */
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/* RGN bits[4:3] indicates the Outer cacheability attributes
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for the memory associated with the translation table walks */
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#define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/
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#define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back Write-Allocate Cacheable. */
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#define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through Cacheable. */
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#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back no Write-Allocate Cacheable. */
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#define ARM_TTBR_ADDR_MASK (0xffffc000) /* only the 18 upper bits are to be used as address */
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#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
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/* Fault status */
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#define ARM_VM_PFE_FS(s) \
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((((s) & ARM_VM_PFE_FS4) >> 6) | ((s) & ARM_VM_PFE_FS3_0))
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#ifndef __ASSEMBLY__
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#include <minix/type.h>
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/* structure used by VM to pass data to the kernel while enabling paging */
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struct vm_ep_data {
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struct mem_map * mem_map;
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vir_bytes data_seg_limit;
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};
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#endif
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#endif /* __SYS_VM_ARM_H__ */
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