311 lines
5.7 KiB
C
311 lines
5.7 KiB
C
/**
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* @file e1000_reg.h
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*
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* @brief Hardware specific registers and flags of the Intel
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* Pro/1000 Gigabit Ethernet card(s).
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*
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* Parts of this code is based on the DragonflyBSD (FreeBSD)
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* implementation, and the fxp driver for Minix 3.
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*
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* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
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* @see fxp.c
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*
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* @author Niek Linnenbank <nieklinnenbank@gmail.com>
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* @date September 2009
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*
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*/
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#ifndef __E1000_REG_H
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#define __E1000_REG_H
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/**
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* @name Controller Registers.
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* @{
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*/
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/** Device Control. */
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#define E1000_REG_CTRL 0x00000
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/** Device Status. */
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#define E1000_REG_STATUS 0x00008
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/** EEPROM Read. */
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#define E1000_REG_EERD 0x00014
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/** Flow Control Address Low. */
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#define E1000_REG_FCAL 0x00028
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/** Flow Control Address High. */
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#define E1000_REG_FCAH 0x0002c
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/** Flow Control Type. */
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#define E1000_REG_FCT 0x00030
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/** Interrupt Cause Read. */
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#define E1000_REG_ICR 0x000c0
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/** Interrupt Mask Set/Read Register. */
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#define E1000_REG_IMS 0x000d0
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/** Receive Control Register. */
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#define E1000_REG_RCTL 0x00100
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/** Transmit Control Register. */
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#define E1000_REG_TCTL 0x00400
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/** Flow Control Transmit Timer Value. */
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#define E1000_REG_FCTTV 0x00170
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/** Receive Descriptor Base Address Low. */
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#define E1000_REG_RDBAL 0x02800
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/** Receive Descriptor Base Address High. */
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#define E1000_REG_RDBAH 0x02804
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/** Receive Descriptor Length. */
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#define E1000_REG_RDLEN 0x02808
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/** Receive Descriptor Head. */
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#define E1000_REG_RDH 0x02810
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/** Receive Descriptor Tail. */
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#define E1000_REG_RDT 0x02818
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/** Transmit Descriptor Base Address Low. */
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#define E1000_REG_TDBAL 0x03800
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/** Transmit Descriptor Base Address High. */
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#define E1000_REG_TDBAH 0x03804
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/** Transmit Descriptor Length. */
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#define E1000_REG_TDLEN 0x03808
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/** Transmit Descriptor Head. */
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#define E1000_REG_TDH 0x03810
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/** Transmit Descriptor Tail. */
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#define E1000_REG_TDT 0x03818
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/** CRC Error Count. */
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#define E1000_REG_CRCERRS 0x04000
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/** RX Error Count. */
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#define E1000_REG_RXERRC 0x0400c
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/** Missed Packets Count. */
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#define E1000_REG_MPC 0x04010
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/** Collision Count. */
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#define E1000_REG_COLC 0x04028
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/** Total Packets Received. */
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#define E1000_REG_TPR 0x040D0
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/** Total Packets Transmitted. */
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#define E1000_REG_TPT 0x040D4
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/** Receive Address Low. */
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#define E1000_REG_RAL 0x05400
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/** Receive Address High. */
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#define E1000_REG_RAH 0x05404
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/** Multicast Table Array. */
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#define E1000_REG_MTA 0x05200
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/**
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* @}
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*/
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/**
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* @name Control Register Bits.
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* @{
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*/
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/** Auto-Speed Detection Enable. */
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#define E1000_REG_CTRL_ASDE (1 << 5)
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/** Link Reset. */
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#define E1000_REG_CTRL_LRST (1 << 3)
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/** Set Link Up. */
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#define E1000_REG_CTRL_SLU (1 << 6)
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/** Invert Los Of Signal. */
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#define E1000_REG_CTRL_ILOS (1 << 7)
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/** Device Reset. */
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#define E1000_REG_CTRL_RST (1 << 26)
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/** VLAN Mode Enable. */
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#define E1000_REG_CTRL_VME (1 << 30)
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/** PHY Reset. */
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#define E1000_REG_CTRL_PHY_RST (1 << 31)
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/**
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* @}
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*/
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/**
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* @name Status Register Bits.
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* @{
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*/
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/** Link Full Duplex Configuration Indication. */
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#define E1000_REG_STATUS_FD (1 << 0)
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/** Link Up Indication. */
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#define E1000_REG_STATUS_LU (1 << 1)
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/** Transmission Paused. */
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#define E1000_REG_STATUS_TXOFF (1 << 4)
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/** Link Speed Setting. */
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#define E1000_REG_STATUS_SPEED ((1 << 6) | (1 << 7))
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/**
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* @}
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*/
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/**
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* @name EEPROM Read Register Bits.
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* @{
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*/
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/** Start Read. */
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#define E1000_REG_EERD_START (1 << 0)
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/** Read Done. */
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#define E1000_REG_EERD_DONE (1 << 4)
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/** Read Address Bit Mask. */
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#define E1000_REG_EERD_ADDR (0xff << 8)
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/** Read Data Bit Mask. */
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#define E1000_REG_EERD_DATA (0xffff << 16)
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/**
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* @}
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*/
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/**
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* @name Interrupt Cause Read.
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* @{
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*/
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/** Transmit Descripts Written Back. */
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#define E1000_REG_ICR_TXDW (1 << 0)
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/** Transmit Queue Empty. */
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#define E1000_REG_ICR_TXQE (1 << 1)
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/** Link Status Change. */
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#define E1000_REG_ICR_LSC (1 << 2)
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/** Receiver Overrun. */
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#define E1000_REG_ICR_RXO (1 << 6)
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/** Receiver Timer Interrupt. */
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#define E1000_REG_ICR_RXT (1 << 7)
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/**
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* @}
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*/
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/**
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* @name Interrupt Mask Set/Read Register Bits.
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* @{
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*/
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/** Transmit Descripts Written Back. */
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#define E1000_REG_IMS_TXDW (1 << 0)
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/** Transmit Queue Empty. */
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#define E1000_REG_IMS_TXQE (1 << 1)
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/** Link Status Change. */
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#define E1000_REG_IMS_LSC (1 << 2)
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/** Receiver FIFO Overrun. */
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#define E1000_REG_IMS_RXO (1 << 6)
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/** Receiver Timer Interrupt. */
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#define E1000_REG_IMS_RXT (1 << 7)
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/**
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* @}
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*/
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/**
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* @name Receive Control Register Bits.
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* @{
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*/
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/** Receive Enable. */
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#define E1000_REG_RCTL_EN (1 << 1)
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/** Multicast Promiscious Enable. */
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#define E1000_REG_RCTL_MPE (1 << 4)
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/** Broadcast Accept Mode. */
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#define E1000_REG_RCTL_BAM (1 << 15)
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/** Receive Buffer Size. */
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#define E1000_REG_RCTL_BSIZE ((1 << 16) | (1 << 17))
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/**
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* @}
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*/
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/**
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* @name Transmit Control Register Bits.
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* @{
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*/
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/** Transmit Enable. */
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#define E1000_REG_TCTL_EN (1 << 1)
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/** Pad Short Packets. */
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#define E1000_REG_TCTL_PSP (1 << 3)
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/**
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* @}
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*/
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/**
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* @name Receive Address High Register Bits.
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* @{
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*/
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/** Receive Address Valid. */
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#define E1000_REG_RAH_AV (1 << 31)
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/**
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* @}
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*/
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/**
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* @name ICH Flash Registers.
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* @see http://gitweb.dragonflybsd.org
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* @{
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*/
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#define ICH_FLASH_GFPREG 0x0000
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#define ICH_FLASH_HSFSTS 0x0004
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#define ICH_FLASH_HSFCTL 0x0006
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#define ICH_FLASH_FADDR 0x0008
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#define ICH_FLASH_FDATA0 0x0010
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#define FLASH_GFPREG_BASE_MASK 0x1FFF
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#define FLASH_SECTOR_ADDR_SHIFT 12
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#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
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#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
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#define ICH_CYCLE_READ 0
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#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
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/**
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* @}
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*/
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#endif /* __E1000_REG_H */
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