84d9c625bf
- Fix for possible unset uid/gid in toproto
- Fix for default mtree style
- Update libelf
- Importing libexecinfo
- Resynchronize GCC, mpc, gmp, mpfr
- build.sh: Replace params with show-params.
This has been done as the make target has been renamed in the same
way, while a new target named params has been added. This new
target generates a file containing all the parameters, instead of
printing it on the console.
- Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
get getservbyport() out of the inner loop
Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
224 lines
8.4 KiB
C
224 lines
8.4 KiB
C
/* $NetBSD: i82489reg.h,v 1.12 2013/01/26 17:37:39 dyoung Exp $ */
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/*-
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* Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Frank van der Linden.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Registers and constants for the 82489DX and Pentium (and up) integrated
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* "local" APIC.
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*/
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#define LAPIC_ID 0x020 /* ID. RW */
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# define LAPIC_ID_MASK 0xff000000
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# define LAPIC_ID_SHIFT 24
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#define LAPIC_VERS 0x030 /* Version. R */
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# define LAPIC_VERSION_MASK 0x000000ff
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# define LAPIC_VERSION_LVT_MASK 0x00ff0000
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# define LAPIC_VERSION_LVT_SHIFT 16
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#define LAPIC_TPRI 0x080 /* Task Prio. RW */
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# define LAPIC_TPRI_MASK 0x000000ff
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# define LAPIC_TPRI_INT_MASK 0x000000f0
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# define LAPIC_TPRI_SUB_MASK 0x0000000f
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#define LAPIC_APRI 0x090 /* Arbitration prio R */
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# define LAPIC_APRI_MASK 0x000000ff
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#define LAPIC_PPRI 0x0a0 /* Processor prio. R */
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#define LAPIC_EOI 0x0b0 /* End Int. W */
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#define LAPIC_RRR 0x0c0 /* Remote read R */
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#define LAPIC_LDR 0x0d0 /* Logical dest. RW */
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#define LAPIC_DFR 0x0e0 /* Dest. format RW */
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# define LAPIC_DFR_MASK 0xf0000000
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# define LAPIC_DFR_FLAT 0xf0000000
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# define LAPIC_DFR_CLUSTER 0x00000000
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#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */
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# define LAPIC_SVR_VECTOR_MASK 0x000000ff
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# define LAPIC_SVR_VEC_FIX 0x0000000f
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# define LAPIC_SVR_VEC_PROG 0x000000f0
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# define LAPIC_SVR_ENABLE 0x00000100
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# define LAPIC_SVR_SWEN 0x00000100
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# define LAPIC_SVR_FOCUS 0x00000200
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# define LAPIC_SVR_FDIS 0x00000200
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#define LAPIC_ISR 0x100 /* In-Service Status */
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#define LAPIC_TMR 0x180 /* Trigger Mode */
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#define LAPIC_IRR 0x200 /* Interrupt Req */
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#define LAPIC_ESR 0x280 /* Err status. R */
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#define LAPIC_ICRLO 0x300 /* Int. cmd. RW */
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# define LAPIC_DLMODE_MASK 0x00000700
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# define LAPIC_DLMODE_FIXED 0x00000000
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# define LAPIC_DLMODE_LOW 0x00000100
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# define LAPIC_DLMODE_SMI 0x00000200
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# define LAPIC_DLMODE_NMI 0x00000400
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# define LAPIC_DLMODE_INIT 0x00000500
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# define LAPIC_DLMODE_STARTUP 0x00000600
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# define LAPIC_DLMODE_EXTINT 0x00000700
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# define LAPIC_DSTMODE_PHYS 0x00000000
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# define LAPIC_DSTMODE_LOG 0x00000800
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# define LAPIC_DLSTAT_BUSY 0x00001000
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# define LAPIC_DLSTAT_IDLE 0x00000000
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# define LAPIC_LEVEL_MASK 0x00004000
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# define LAPIC_LEVEL_ASSERT 0x00004000
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# define LAPIC_LEVEL_DEASSERT 0x00000000
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# define LAPIC_TRIGGER_MASK 0x00008000
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# define LAPIC_TRIGGER_EDGE 0x00000000
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# define LAPIC_TRIGGER_LEVEL 0x00008000
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# define LAPIC_DEST_MASK 0x000c0000
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# define LAPIC_DEST_DEFAULT 0x00000000
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# define LAPIC_DEST_SELF 0x00040000
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# define LAPIC_DEST_ALLINCL 0x00080000
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# define LAPIC_DEST_ALLEXCL 0x000c0000
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#define LAPIC_ICRHI 0x310 /* Int. cmd. RW */
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#define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */
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# define LAPIC_LVTT_VEC_MASK 0x000000ff
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# define LAPIC_LVTT_DS 0x00001000
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# define LAPIC_LVTT_M 0x00010000
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# define LAPIC_LVTT_TM 0x00020000
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#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) */
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#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) */
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#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */
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# define LAPIC_LVT_MASKED 0x00010000
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# define LAPIC_LVT_LEVTRIG 0x00008000
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# define LAPIC_LVT_REMOTE_IRR 0x00004000
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# define LAPIC_INP_POL 0x00002000
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# define LAPIC_PEND_SEND 0x00001000
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#define LAPIC_LVINT1 0x360 /* Loc.vec (LINT1) RW */
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#define LAPIC_LVERR 0x370 /* Loc.vec (ERROR) RW */
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#define LAPIC_ICR_TIMER 0x380 /* Initial count RW */
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#define LAPIC_CCR_TIMER 0x390 /* Current count RO */
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#define LAPIC_DCR_TIMER 0x3e0 /* Divisor config register */
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# define LAPIC_DCRT_DIV1 0x0b
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# define LAPIC_DCRT_DIV2 0x00
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# define LAPIC_DCRT_DIV4 0x01
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# define LAPIC_DCRT_DIV8 0x02
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# define LAPIC_DCRT_DIV16 0x03
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# define LAPIC_DCRT_DIV32 0x08
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# define LAPIC_DCRT_DIV64 0x09
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# define LAPIC_DCRT_DIV128 0x0a
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#define LAPIC_MSIADDR_BASE 0xfee00000
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#define LAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
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#define LAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
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#define LAPIC_MSIADDR_RH __BIT(3)
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#define LAPIC_MSIADDR_DM __BIT(2)
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#define LAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
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#define LAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0)
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#define LAPIC_MSIDATA_DM_MASK __BITS(10, 8)
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#define LAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_SMI __SHIFTIN(2, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_NMI __SHIFTIN(4, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_INIT __SHIFTIN(5, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, LAPIC_MSIDATA_DM_MASK)
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#define LAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11)
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#define LAPIC_MSIDATA_LEVEL_MASK __BIT(14)
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#define LAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, LAPIC_MSIDATA_LEVEL_MASK)
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#define LAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, LAPIC_MSIDATA_LEVEL_MASK)
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#define LAPIC_MSIDATA_TRGMODE_MASK __BIT(15)
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#define LAPIC_MSIDATA_TRGMODE_EDGE __SHIFTIN(0, LAPIC_MSIDATA_TRGMODE_MASK)
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#define LAPIC_MSIDATA_TRGMODE_LEVEL __SHIFTIN(1, LAPIC_MSIDATA_TRGMODE_MASK)
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#define LAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16)
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#define LAPIC_BASE 0xfee00000
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#define LAPIC_IRQ_MASK(i) (1 << ((i) + 1))
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/* Extended APIC registers, valid when CPUID features4 EAPIC is present */
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#define LEAPIC_FR 0x400 /* Feature register */
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# define LEAPIC_FR_ELC __BITS(23,16) /* Ext. Lvt Count RO */
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# define LEAPIC_FR_EIDCAP __BIT(2) /* Ext. Apic ID Cap. RO */
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# define LEAPIC_FR_SEIOCAP __BIT(1) /* Specific EOI Cap. RO */
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# define LEAPIC_FR_IERCAP __BIT(0) /* Intr. Enable Reg. RO */
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#define LEAPIC_CR 0x410 /* Control Register */
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# define LEAPIC_CR_EID_ENABLE __BIT(2) /* Ext. Apic ID enable */
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# define LEAPIC_CR_SEOI_ENABLE __BIT(1) /* Specific EOI enable */
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# define LEAPIC_CR_IER_ENABLE __BIT(0) /* Enable writes to IER */
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#define LEAPIC_SEOIR 0x420 /* Specific EOI Register */
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# define LEAPIC_SEOI_VEC __BITS(7,0)
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#define LEAPIC_IER_480 0x480 /* Interrupts 0-31 */
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#define LEAPIC_IER_490 0x490 /* Interrupts 32-63 */
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#define LEAPIC_IER_4B0 0x4B0 /* Interrupts 64-95 */
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#define LEAPIC_IER_4C0 0x4C0 /* Interrupts 96-127 */
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#define LEAPIC_IER_4D0 0x4D0 /* Interrupts 128-159 */
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#define LEAPIC_IER_4E0 0x4E0 /* Interrupts 160-191 */
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#define LEAPIC_IER_4F0 0x4F0 /* Interrupts 192-255 */
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/* Extended Local Vector Table Entries */
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#define LEAPIC_LVTR_500 0x500
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#define LEAPIC_LVTR_504 0x504
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#define LEAPIC_LVTR_508 0x508
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#define LEAPIC_LVTR_50C 0x50C
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#define LEAPIC_LVTR_510 0x510
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#define LEAPIC_LVTR_514 0x514
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#define LEAPIC_LVTR_518 0x518
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#define LEAPIC_LVTR_51C 0x51C
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#define LEAPIC_LVTR_520 0x520
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#define LEAPIC_LVTR_524 0x524
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#define LEAPIC_LVTR_528 0x528
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#define LEAPIC_LVTR_52C 0x52C
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#define LEAPIC_LVTR_530 0x530
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# define LEAPIC_LVTR_MASK __BIT(16) /* interrupt masked RW */
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# define LEAPIC_LVTR_DSTAT __BIT(12) /* delivery state RO */
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# define LEAPIC_LVTR_MSGTYPE __BITS(10,8) /* Message type */
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# define LEAPIC_LVTR_VEC __BITS(7,0) /* the intr. vector */
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/*
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* Model specific registers
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*/
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#define LAPIC_MSR 0x001b
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# define LAPIC_MSR_BSP 0x00000100 /* boot processor */
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# define LAPIC_MSR_ENABLE_x2 0x00000400 /* x2APIC mode */
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# define LAPIC_MSR_ENABLE 0x00000800 /* software enable */
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# define LAPIC_MSR_ADDR 0xfffff000 /* physical address */
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