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generified vhdl template for new BlockRam, see #232

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hneemann 2019-01-24 17:26:25 +01:00
parent c0b139741e
commit 0264c225eb
1 changed files with 5 additions and 3 deletions
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8
src/main/resources/vhdl2/DIG_BlockRAMDualPortMasked.tem
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@ -3,14 +3,16 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all; USE ieee.numeric_std.all;
<? <?
entityName := "BlockRam_D"+elem.Bits+"A"+elem.AddrBits; entityName := "BlockRam_D"+elem.Bits;
maskBits := elem.Bits / 8; maskBits := elem.Bits / 8;
?> ?>
entity <?=entityName?> is entity <?=entityName?> is
generic (
AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
port ( port (
D: out std_logic_vector (<?=elem.Bits-1?> downto 0); D: out std_logic_vector (<?=elem.Bits-1?> downto 0);
A: in std_logic_vector (<?=elem.AddrBits-1?> downto 0); A: in std_logic_vector ((AddrBits-1) downto 0);
Din: in std_logic_vector (<?=elem.Bits-1?> downto 0); Din: in std_logic_vector (<?=elem.Bits-1?> downto 0);
str: in <? str: in <?
if (maskBits=1) { if (maskBits=1) {
@ -22,7 +24,7 @@ entity <?=entityName?> is
end <?=entityName?>; end <?=entityName?>;
architecture Behavioral of <?=entityName?> is architecture Behavioral of <?=entityName?> is
type memoryType is array(0 to <?=(1<<elem.AddrBits)-1?>) of std_logic_vector(<?=elem.Bits-1?> downto 0); type memoryType is array(0 to (2**AddrBits)-1) of std_logic_vector(<?=elem.Bits-1?> downto 0);
signal memory : memoryType; signal memory : memoryType;
signal rData : std_logic_vector (<?=elem.Bits-1?> downto 0) := (others => '0'); signal rData : std_logic_vector (<?=elem.Bits-1?> downto 0) := (others => '0');
begin begin