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enables at least one verilog test, see #394

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hneemann 2019-12-15 13:46:29 +01:00
parent a4a3ff5d60
commit 13c555fbd1
1 changed files with 7 additions and 5 deletions
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12
src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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@ -72,17 +72,19 @@ public class VerilogSimulatorTest extends TestCase {
} }
} }
/*
public void testInSimulatorInOut() throws Exception { public void testInSimulatorInOut() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test/pinControl"); File examples = new File(Resources.getRoot(), "/dig/test/pinControl");
try { try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples); int tested = new FileScanner(f -> {
if (!f.getName().equals("uniTest.dig"))
checkVerilogExport(f);
}).noOutput().scan(examples);
assertEquals(2, tested); assertEquals(2, tested);
assertEquals(2, testBenches); assertEquals(1, testBenches);
} catch (FileScanner.SkipAllException e) { } catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok // if iverilog is not installed its also ok
} }
}/**/ }
public void testDistributedInSimulator() throws Exception { public void testDistributedInSimulator() throws Exception {
@ -142,7 +144,7 @@ public class VerilogSimulatorTest extends TestCase {
try { try {
File srcFile = new File(dir, file.getName() File srcFile = new File(dir, file.getName()
.replace('.', '_') .replace('.', '_')
.replace('-', '_')+ ".v"); .replace('-', '_') + ".v");
CodePrinter out = new CodePrinter(srcFile); CodePrinter out = new CodePrinter(srcFile);
try (VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out)) { try (VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out)) {
gen.export(br.getCircuit()); gen.export(br.getCircuit());