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Fixed a bug in the VerilogClockExample.config.

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hneemann 2019-05-20 21:39:27 +02:00
parent eeb969c8bd
commit 29b4cabd6c
2 changed files with 7 additions and 20 deletions
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26
src/main/dig/hdl/BASYS3_lightchase.dig
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@ -3,16 +3,6 @@
<version>1</version> <version>1</version>
<attributes/> <attributes/>
<visualElements> <visualElements>
<visualElement>
<elementName>Text</elementName>
<elementAttributes>
<entry>
<string>Description</string>
<string>Board: BASYS3</string>
</entry>
</elementAttributes>
<pos x="1040" y="340"/>
</visualElement>
<visualElement> <visualElement>
<elementName>Add</elementName> <elementName>Add</elementName>
<elementAttributes> <elementAttributes>
@ -117,18 +107,16 @@ repeat(16) C bits(16,1&lt;&lt;n)
<elementAttributes> <elementAttributes>
<entry> <entry>
<string>Description</string> <string>Description</string>
<string>Export this file to VHDL and use Xilinx Vivado to create the bitstream. <string>Select the file &quot;BASYS3.config&quot; as toolchain configuration in the settings.
Then use the new main menu items to create the Verilog or VHDL code and
use Vivado to create the bit stream.
Also add the created constraints file to the vivado project to assign {{de Wählen Sie die Datei &quot;BASYS3.config&quot; als Toolchain Konfiguration in
the pins correctly. den EInstellungen aus. Mit den neuen Menüeinträgen können Sie dann Verilog
{{de Exportieren Sie diese Datei zu VHDL und verwenden Sie Xilinx Vivado, oder VHDL Code erzeugen und mit Vivado den Bitstream erzeugen.}}</string>
um den Bitstream zu erstellen.
Fügen Sie auch die erstellte Constraint-Datei dem Vivado-Projekt hinzu, um
die Pins korrekt zuzuordnen.}}</string>
</entry> </entry>
</elementAttributes> </elementAttributes>
<pos x="400" y="-340"/> <pos x="380" y="-340"/>
</visualElement> </visualElement>
<visualElement> <visualElement>
<elementName>Out</elementName> <elementName>Out</elementName>

1
src/main/dig/hdl/VerilogClockExample.config
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@ -6,7 +6,6 @@
<params> <params>
<!-- used by the Vivado project template --> <!-- used by the Vivado project template -->
<param name="chip">xc7a35ticpg236-1L</param> <param name="chip">xc7a35ticpg236-1L</param>
<param name="extension">.v</param>
</params> </params>
<files> <files>
<file name="clockGenerator.v" overwrite="true" filter="true"> <file name="clockGenerator.v" overwrite="true" filter="true">