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some cleanup

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This commit is contained in:
hneemann 2018-03-24 18:04:33 +01:00
parent 812302bcf7
commit 57228748d4
5 changed files with 6 additions and 75 deletions
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4
src/main/resources/vhdl2/DIG_Counter.tem
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@ -12,7 +12,7 @@ entity DIG_Counter is
clr: in std_logic );
end DIG_Counter;
architecture DIG_Counter_arch of DIG_Counter is
architecture Behavioral of DIG_Counter is
signal count : std_logic_vector((Bits-1) downto 0) := (others => '0');
begin
process (C, clr, en)
@ -28,4 +28,4 @@ begin
p_out <= count;
ovf <= en when count = ((2**Bits)-1) else '0';
end DIG_Counter_arch;
end Behavioral;

4
src/main/resources/vhdl2/DIG_Demultiplexer.tem
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@ -20,9 +20,9 @@ entity <?=entityName?> is
p_in: in <?= vhdl.genericType(elem.Bits)?> );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
architecture Behavioral of <?=entityName?> is
begin
<?- for (i:=0;i<outputs;i++) {?>
out_<?=i?> <= p_in when sel = <?= vhdl.value(i,elem.'Selector Bits')?> else <?= vhdl.zero(elem.Bits)?>;
<?- } ?>
end <?=entityName?>_arch;
end Behavioral;

23
src/main/resources/vhdl2/DIG_Not.tem
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@ -1,23 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (elem.Bits=1)
entityName:="NOT_GATE";
else
entityName:="NOT_GATE_BUS";
?>
entity <?=entityName?> is
<?vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
PORT_in: in <?=vhdl.genericType(elem.Bits)?> );
<?vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_out <= NOT( PORT_in );
end <?=entityName?>_arch;

46
src/main/resources/vhdl2/DIG_Operate.tem
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@ -1,46 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (param.inv)
entityName:="N"+param.op;
else
entityName:=param.op;
if (elem.Bits=1)
entityName=entityName+"_GATE_"+elem.Inputs;
else
entityName=entityName+"_GATE_BUS_"+elem.Inputs;
?>
entity <?=entityName?> is
<?vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
<? for (i:=0;i<elem.Inputs;i++) { ?>
PORT_In_<?=i+1?>: in <?
print(vhdl.genericType(elem.Bits));
if (i=elem.Inputs-1) print(" )");
?>;
<? } ?>
<?vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_out <= <?
if (param.inv)
print("NOT (");
for (i:=0;i<elem.Inputs;i++) {
print("PORT_In_",i+1);
if (i<elem.Inputs-1)
print(" ",param.op," ");
}
if (param.inv)
print(" )");
?>;
end <?=entityName?>_arch;

4
src/main/resources/vhdl2/DIG_RAMDualAccess.tem
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@ -17,7 +17,7 @@ entity DIG_RAMDualAccess is
n2A: in std_logic_vector ((AddrBits-1) downto 0) );
end DIG_RAMDualAccess;
architecture DIG_RAMDualAccess_arch of DIG_RAMDualAccess is
architecture Behavioral of DIG_RAMDualAccess is
-- CAUTION: uses distributed RAM
type memoryType is array(0 to (2**AddrBits)-1) of STD_LOGIC_VECTOR((Bits-1) downto 0);
signal memory : memoryType;
@ -30,4 +30,4 @@ begin
end process;
n1D <= memory(to_integer(unsigned(n1A))) when ld='1' else (others => 'Z');
n2D <= memory(to_integer(unsigned(n2A)));
end DIG_RAMDualAccess_arch;
end Behavioral;