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added vivado tool chain support

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This commit is contained in:
hneemann 2019-05-14 23:34:43 +02:00
parent 1d1b4f60f1
commit 6c2bec3b69
14 changed files with 433 additions and 73 deletions
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1
distribution/Assembly.xml
View File

@ -121,6 +121,7 @@
<outputDirectory>/examples/hdl/</outputDirectory>
<includes>
<include>*.dig</include>
<include>*.xml</include>
</includes>
</fileSet>
<fileSet>

68
src/main/dig/hdl/BASYS3.xml Normal file
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@ -0,0 +1,68 @@
<ide name="BASYS 3">
<commands>
<command name="Export to Vivado" requires="vhdl" filter="false">
</command>
</commands>
<files>
<file name="&lt;?=shortname?&gt;_constraints.xdc" overwrite="true" filter="true">
<content><![CDATA[<?
port := 0;
for (i:=0; i<sizeOf(hdl.ports);i++) {
port=hdl.ports[i];
if (port.bits=1) {
print("set_property PACKAGE_PIN "+port.pin+" [get_ports "+port.name+"]\n");
print("set_property IOSTANDARD LVCMOS33 [get_ports "+port.name+"]\n\n");
if (port.clock) {
print("create_clock -add -name sys_clk_pin -period 10 -waveform {0 5} [get_ports "+port.name+"]\n\n");
}
} else {
panic("multi bit ports are not yet supported!");
}
}
print("set_property CFGBVS VCCO [current_design]\n");
print("set_property CONFIG_VOLTAGE 3.3 [current_design]\n");
?>]]></content>
</file>
<file name="vivado/&lt;?=shortname?&gt;.xpr" overwrite="true" filter="true">
<content><![CDATA[<?print("<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n");?>
<!-- Created by Digital -->
<Project Version="7" Minor="20" Path="<?=dir?>/vivado/<?=shortname?>.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Part" Val="xc7a35ticpg236-1L"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../<?=shortname?>.vhdl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="main"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../<?=shortname?>_constraints.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
</FileSets>
</Project>]]></content>
</file>
</files>
</ide>

174
src/main/dig/hdl/TinyFPGA_BX_Config.xml Normal file
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@ -0,0 +1,174 @@
<ide name="TinyFPGA BX">
<commands>
<command name="Build" requires="verilog" filter="false">
<arg>make</arg>
</command>
<command name="Program" requires="verilog" filter="false">
<arg>make</arg>
<arg>prog</arg>
</command>
</commands>
<files>
<file name="Makefile" overwrite="false" filter="true">
<content># Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
#
# The following license is from the icestorm project and specifically applies to this file only:
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED &quot;AS IS&quot; AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
PROJ = &lt;?=shortname?&gt;
PIN_DEF = pins.pcf
DEVICE = lp8k
#all: $(PROJ).rpt $(PROJ).bin
all: $(PROJ).bin
%.blif: %.v
yosys -p &apos;synth_ice40 -top $(PROJ) -blif $@&apos; $&lt;
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P cm81 -o $@ -p $^
%.bin: %.asc
icepack $&lt; $@
%.rpt: %.asc
icetime -d $(DEVICE) -C C:\Users\helmut.neemann\.apio\packages\toolchain-icestorm\share\icebox -mtr $@ $&lt;
%_tb: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb
vvp -N $&lt; +vcd=$@
%_syn.v: %.blif
yosys -p &apos;read_blif -wideports $^; write_verilog $@&apos;
%_syntb: %_tb.v %_syn.v
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
%_syntb.vcd: %_syntb
vvp -N $&lt; +vcd=$@
prog: $(PROJ).bin
tinyprog -p $&lt;
sudo-prog: $(PROJ).bin
@echo &apos;Executing prog as root!!!&apos;
sudo tinyprog -p $&lt;
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean</content>
</file>
<file name="pins.pcf" overwrite="false" filter="false">
<content>###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the &lt;project name&gt; project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input</content>
</file>
</files>
</ide>

80
src/main/dig/sequential/RS-T.dig
View File

@ -1,6 +1,7 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>NOr</elementName>
@ -20,7 +21,7 @@
<string>S</string>
</entry>
</elementAttributes>
<pos x="1080" y="640"/>
<pos x="960" y="640"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
@ -30,7 +31,7 @@
<string>C</string>
</entry>
</elementAttributes>
<pos x="1080" y="540"/>
<pos x="960" y="540"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
@ -70,22 +71,22 @@
<string>R</string>
</entry>
</elementAttributes>
<pos x="1080" y="440"/>
<pos x="960" y="440"/>
</visualElement>
<visualElement>
<elementName>And</elementName>
<elementAttributes/>
<pos x="1240" y="520"/>
</visualElement>
<visualElement>
<elementName>Delay</elementName>
<elementAttributes/>
<pos x="1180" y="520"/>
</visualElement>
<visualElement>
<elementName>Not</elementName>
<elementAttributes/>
<pos x="1120" y="520"/>
<elementAttributes>
<entry>
<string>wideShape</string>
<boolean>true</boolean>
</entry>
</elementAttributes>
<pos x="1000" y="520"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
@ -104,6 +105,26 @@ X 0 X 1 0
</elementAttributes>
<pos x="1500" y="640"/>
</visualElement>
<visualElement>
<elementName>Not</elementName>
<elementAttributes>
<entry>
<string>wideShape</string>
<boolean>true</boolean>
</entry>
</elementAttributes>
<pos x="1080" y="520"/>
</visualElement>
<visualElement>
<elementName>Not</elementName>
<elementAttributes>
<entry>
<string>wideShape</string>
<boolean>true</boolean>
</entry>
</elementAttributes>
<pos x="1160" y="520"/>
</visualElement>
</visualElements>
<wires>
<wire>
@ -127,11 +148,11 @@ X 0 X 1 0
<p2 x="1560" y="480"/>
</wire>
<wire>
<p1 x="1080" y="640"/>
<p1 x="960" y="640"/>
<p2 x="1340" y="640"/>
</wire>
<wire>
<p1 x="1100" y="560"/>
<p1 x="980" y="560"/>
<p2 x="1240" y="560"/>
</wire>
<wire>
@ -155,20 +176,24 @@ X 0 X 1 0
<p2 x="1560" y="600"/>
</wire>
<wire>
<p1 x="1080" y="440"/>
<p1 x="960" y="440"/>
<p2 x="1340" y="440"/>
</wire>
<wire>
<p1 x="1100" y="520"/>
<p2 x="1120" y="520"/>
<p1 x="980" y="520"/>
<p2 x="1000" y="520"/>
</wire>
<wire>
<p1 x="1220" y="520"/>
<p2 x="1240" y="520"/>
</wire>
<wire>
<p1 x="1160" y="520"/>
<p2 x="1180" y="520"/>
<p1 x="1060" y="520"/>
<p2 x="1080" y="520"/>
</wire>
<wire>
<p1 x="1140" y="520"/>
<p2 x="1160" y="520"/>
</wire>
<wire>
<p1 x="1400" y="620"/>
@ -183,8 +208,8 @@ X 0 X 1 0
<p2 x="1320" y="540"/>
</wire>
<wire>
<p1 x="1080" y="540"/>
<p2 x="1100" y="540"/>
<p1 x="960" y="540"/>
<p2 x="980" y="540"/>
</wire>
<wire>
<p1 x="1540" y="480"/>
@ -194,6 +219,14 @@ X 0 X 1 0
<p1 x="1540" y="560"/>
<p2 x="1540" y="600"/>
</wire>
<wire>
<p1 x="980" y="520"/>
<p2 x="980" y="540"/>
</wire>
<wire>
<p1 x="980" y="540"/>
<p2 x="980" y="560"/>
</wire>
<wire>
<p1 x="1320" y="480"/>
<p2 x="1320" y="540"/>
@ -210,13 +243,6 @@ X 0 X 1 0
<p1 x="1420" y="500"/>
<p2 x="1420" y="520"/>
</wire>
<wire>
<p1 x="1100" y="520"/>
<p2 x="1100" y="540"/>
</wire>
<wire>
<p1 x="1100" y="540"/>
<p2 x="1100" y="560"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>

6
src/main/java/de/neemann/digital/core/element/Keys.java
View File

@ -464,7 +464,7 @@ public final class Keys {
* enables the MAC mouse mode
*/
public static final Key<Boolean> SETTINGS_MAC_MOUSE
= new Key<>("macMouse", Screen.isMac()).setRequiresRestart().setSecondary();
= new Key<>("macMouse", Screen.isMac()).setRequiresRestart();
/**
* output format for numbers
@ -781,7 +781,7 @@ public final class Keys {
/**
* Stores the IDE settings file
*/
public static final Key<File> SETTINGS_IDE_CONFIG =
new Key.KeyFile("ideSettings", new File("")).setSecondary().setRequiresRestart();
public static final Key<File> SETTINGS_TOOLCHAIN_CONFIG =
new Key.KeyFile("toolChainConfig", new File("")).setSecondary().setRequiresRestart();
}

2
src/main/java/de/neemann/digital/gui/Main.java
View File

@ -294,7 +294,7 @@ public final class Main extends JFrame implements ClosingWindowListener.ConfirmS
private void checkIDEIntegration(MainBuilder builder, JMenuBar menuBar) {
if (builder.mainFrame) {
File f = Settings.getInstance().get(Keys.SETTINGS_IDE_CONFIG);
File f = Settings.getInstance().get(Keys.SETTINGS_TOOLCHAIN_CONFIG);
if (f.getPath().length() > 0) {
try {
menuBar.add(

2
src/main/java/de/neemann/digital/gui/Settings.java
View File

@ -58,7 +58,7 @@ public final class Settings implements AttributeListener {
intList.add(Keys.SETTINGS_ATMISP);
intList.add(Keys.SETTINGS_GHDL_PATH);
intList.add(Keys.SETTINGS_IVERILOG_PATH);
intList.add(Keys.SETTINGS_IDE_CONFIG);
intList.add(Keys.SETTINGS_TOOLCHAIN_CONFIG);
intList.add(Keys.SETTINGS_FONT_SCALING);
intList.add(Keys.SETTINGS_MAC_MOUSE);

3
src/main/java/de/neemann/digital/hdl/hgs/Tokenizer.java
View File

@ -253,6 +253,9 @@ class Tokenizer {
case 't':
c = '\t';
break;
case '"':
c = '"';
break;
default:
throw new IOException("not allowed in string: \\" + (char) c);
}

10
src/main/java/de/neemann/digital/hdl/verilog2/VerilogGenerator.java
View File

@ -35,6 +35,7 @@ public class VerilogGenerator implements Closeable {
private final CodePrinter out;
private ArrayList<File> testBenches;
private boolean useClockIntegration = true;
private HDLModel model;
/**
* Creates a new exporter
@ -66,7 +67,7 @@ public class VerilogGenerator implements Closeable {
if (board != null && useClockIntegration)
clockIntegrator = board.getClockIntegrator();
HDLModel model = new HDLModel(library).create(circuit, clockIntegrator);
model = new HDLModel(library).create(circuit, clockIntegrator);
for (HDLCircuit hdlCircuit : model)
hdlCircuit.applyDefaultOptimizations();
@ -155,6 +156,13 @@ public class VerilogGenerator implements Closeable {
out.close();
}
/**
* @return the used hdl model
*/
public HDLModel getModel() {
return model;
}
/**
* Disables the clock integration.
* Used only for the tests.

10
src/main/java/de/neemann/digital/hdl/vhdl2/VHDLGenerator.java
View File

@ -39,6 +39,7 @@ public class VHDLGenerator implements Closeable {
private final CodePrinter out;
private ArrayList<File> testBenches;
private boolean useClockIntegration = true;
private HDLModel model;
/**
* Creates a new exporter
@ -70,7 +71,7 @@ public class VHDLGenerator implements Closeable {
if (board != null && useClockIntegration)
clockIntegrator = board.getClockIntegrator();
HDLModel model = new HDLModel(library).create(circuit, clockIntegrator);
model = new HDLModel(library).create(circuit, clockIntegrator);
for (HDLCircuit hdlCircuit : model)
hdlCircuit.applyDefaultOptimizations();
@ -161,4 +162,11 @@ public class VHDLGenerator implements Closeable {
useClockIntegration = false;
return this;
}
/**
* @return the hdl model
*/
public HDLModel getModel() {
return model;
}
}

132
src/main/java/de/neemann/digital/ide/Configuration.java
View File

@ -11,10 +11,10 @@ import de.neemann.digital.core.extern.ProcessStarter;
import de.neemann.digital.draw.elements.Circuit;
import de.neemann.digital.draw.library.ElementLibrary;
import de.neemann.digital.gui.SaveAsHelper;
import de.neemann.digital.hdl.hgs.Context;
import de.neemann.digital.hdl.hgs.HGSEvalException;
import de.neemann.digital.hdl.hgs.Parser;
import de.neemann.digital.hdl.hgs.ParserException;
import de.neemann.digital.hdl.hgs.*;
import de.neemann.digital.hdl.model2.HDLCircuit;
import de.neemann.digital.hdl.model2.HDLModel;
import de.neemann.digital.hdl.model2.HDLPort;
import de.neemann.digital.hdl.printer.CodePrinter;
import de.neemann.digital.hdl.verilog2.VerilogGenerator;
import de.neemann.digital.hdl.vhdl2.VHDLGenerator;
@ -80,7 +80,8 @@ public final class Configuration {
private transient FilenameProvider filenameProvider;
private transient CircuitProvider circuitProvider;
private transient LibraryProvider libraryProvider;
private transient FileWriter fileWriter;
private transient IOInterface ioInterface;
private Configuration() {
files = new ArrayList<>();
@ -120,8 +121,8 @@ public final class Configuration {
return this;
}
Configuration setFileWriter(FileWriter fileWriter) {
this.fileWriter = fileWriter;
Configuration setIoInterface(IOInterface ioInterface) {
this.ioInterface = ioInterface;
return this;
}
@ -137,8 +138,8 @@ public final class Configuration {
return menu;
}
private void checkFilesToCreate(File fileToExecute) throws HGSEvalException, IOException, ParserException {
Context context = createContext(fileToExecute);
private void checkFilesToCreate(File fileToExecute, HDLModel hdlModel) throws HGSEvalException, IOException, ParserException {
Context context = createContext(fileToExecute, hdlModel);
if (files != null)
for (FileToCreate f : files) {
@ -156,25 +157,28 @@ public final class Configuration {
content = context.toString();
}
try (OutputStream out = getFileWriter().getOutputStream(filename)) {
try (OutputStream out = getIoInterface().getOutputStream(filename)) {
out.write(content.getBytes());
}
}
}
}
private Context createContext(File fileToExecute) throws HGSEvalException {
return new Context()
private Context createContext(File fileToExecute, HDLModel hdlModel) throws HGSEvalException {
final Context context = new Context()
.declareVar("path", fileToExecute.getPath())
.declareVar("dir", fileToExecute.getParentFile())
.declareVar("name", fileToExecute.getName())
.declareVar("shortname", createShortname(fileToExecute.getName()));
if (hdlModel != null)
context.declareVar("hdl", new ModelAccess(hdlModel.getMain()));
return context;
}
private FileWriter getFileWriter() {
if (fileWriter == null)
fileWriter = new DefaultFileWriter();
return fileWriter;
private IOInterface getIoInterface() {
if (ioInterface == null)
ioInterface = new DefaultIOInterface();
return ioInterface;
}
private String createShortname(String name) {
@ -184,22 +188,22 @@ public final class Configuration {
return name;
}
private void writeHDL(String hdl, File digFile) throws IOException {
private HDLModel writeHDL(String hdl, File digFile) throws IOException {
switch (hdl) {
case "verilog":
File verilogFile = SaveAsHelper.checkSuffix(digFile, "v");
final CodePrinter verilogPrinter = new CodePrinter(getFileWriter().getOutputStream(verilogFile));
final CodePrinter verilogPrinter = new CodePrinter(getIoInterface().getOutputStream(verilogFile));
try (VerilogGenerator vlog = new VerilogGenerator(libraryProvider.getCurrentLibrary(), verilogPrinter)) {
vlog.export(circuitProvider.getCurrentCircuit());
return vlog.getModel();
}
break;
case "vhdl":
File vhdlFile = SaveAsHelper.checkSuffix(digFile, "vhdl");
final CodePrinter vhdlPrinter = new CodePrinter(getFileWriter().getOutputStream(vhdlFile));
final CodePrinter vhdlPrinter = new CodePrinter(getIoInterface().getOutputStream(vhdlFile));
try (VHDLGenerator vlog = new VHDLGenerator(libraryProvider.getCurrentLibrary(), vhdlPrinter)) {
vlog.export(circuitProvider.getCurrentCircuit());
return vlog.getModel();
}
break;
default:
throw new IOException(Lang.get("err_hdlNotKnown_N", hdl));
}
@ -215,25 +219,26 @@ public final class Configuration {
if (digFile != null) {
try {
HDLModel hdlModel = null;
if (command.needsHDL())
writeHDL(command.getHDL(), digFile);
hdlModel = writeHDL(command.getHDL(), digFile);
checkFilesToCreate(digFile);
checkFilesToCreate(digFile, hdlModel);
String[] args = command.getArgs();
if (command.isFilter()) {
final int argCount = command.getArgs().length;
Context context = createContext(digFile);
Context context = createContext(digFile, hdlModel);
for (int i = 0; i < argCount; i++) {
context.clearOutput();
new Parser(args[i]).parse().execute(context);
args[i] = context.toString();
}
}
getFileWriter().startProcess(digFile.getParentFile(), args);
if (args != null)
getIoInterface().startProcess(digFile.getParentFile(), args);
} catch (Exception e) {
getFileWriter().showError(command, e);
getIoInterface().showError(command, e);
}
}
}
@ -289,7 +294,7 @@ public final class Configuration {
/**
* Interface used to write a file
*/
public interface FileWriter {
public interface IOInterface {
/**
* Creates an output stream
@ -318,10 +323,15 @@ public final class Configuration {
void showError(Command command, Exception e);
}
private static final class DefaultFileWriter implements FileWriter {
private static final class DefaultIOInterface implements IOInterface {
@Override
public OutputStream getOutputStream(File filename) throws FileNotFoundException {
public OutputStream getOutputStream(File filename) throws IOException {
final File parentFile = filename.getParentFile();
if (!parentFile.exists()) {
if (!parentFile.mkdirs())
throw new IOException("could not create "+parentFile);
}
return new FileOutputStream(filename);
}
@ -335,4 +345,66 @@ public final class Configuration {
new ErrorMessage(Lang.get("msg_errorStartCommand_N", command.getName())).addCause(e).show();
}
}
private static final class ModelAccess implements HGSMap {
private final HDLCircuit hdlCircuit;
private ModelAccess(HDLCircuit hdlCircuit) {
this.hdlCircuit = hdlCircuit;
}
@Override
public Object hgsMapGet(String key) throws HGSEvalException {
switch (key) {
case "ports":
return new PortsArray(hdlCircuit.getPorts());
default:
throw new HGSEvalException("field " + key + " not found!");
}
}
}
private static final class PortsArray implements HGSArray {
private final ArrayList<HDLPort> ports;
private PortsArray(ArrayList<HDLPort> ports) {
this.ports = ports;
}
@Override
public int hgsArraySize() {
return ports.size();
}
@Override
public Object hgsArrayGet(int i) {
return new Port(ports.get(i));
}
}
private static final class Port implements HGSMap {
private final HDLPort hdlPort;
private Port(HDLPort hdlPort) {
this.hdlPort = hdlPort;
}
@Override
public Object hgsMapGet(String key) throws HGSEvalException {
switch (key) {
case "dir":
return hdlPort.getDirection().name();
case "name":
return hdlPort.getName();
case "bits":
return hdlPort.getBits();
case "pin":
return hdlPort.getPinNumber();
case "clock":
return hdlPort.isClock();
default:
throw new HGSEvalException("field " + key + " not found!");
}
}
}
}

4
src/main/resources/lang/lang_de.xml
View File

@ -1332,8 +1332,8 @@ Sind evtl. die Namen der Variablen nicht eindeutig?</string>
<string name="key_enabled">Aktiviert</string>
<string name="key_enabled_tt">Aktiviert oder deaktiviert diese Komponente.</string>
<string name="key_ideSettings">IDE-Einstellungen</string>
<string name="key_ideSettings_tt">Kann für eine IDE-Integration verwendet werden.
<string name="key_toolChainConfig">Tool Chain</string>
<string name="key_toolChainConfig_tt">Kann für eine Integration einer externen Tool Chain verwendet werden.
Erlaubt den Start externer Tools, um z.B. einen FPGA zu programmieren o.ä.</string>
<string name="mod_insertWire">Leitung eingefügt.</string>

4
src/main/resources/lang/lang_en.xml
View File

@ -1320,8 +1320,8 @@
<string name="key_enabled">Enabled</string>
<string name="key_enabled_tt">Enables or disables this component.</string>
<string name="key_ideSettings">IDE settings</string>
<string name="key_ideSettings_tt">Used to configurate an IDE integration.
<string name="key_toolChainConfig">Tool Chain</string>
<string name="key_toolChainConfig_tt">Used to configurate an integration of a tool chain.
Allows the start of external tools, e.g. to program an FPGA or similar.</string>
<string name="mod_insertWire">Inserted wire.</string>

10
src/test/java/de/neemann/digital/ide/ConfigurationTest.java
View File

@ -35,12 +35,12 @@ public class ConfigurationTest extends TestCase {
ToBreakRunner br = new ToBreakRunner(new File(Resources.getRoot(), "dig/hdl/negSimple.dig"));
final TestFileWriter fileWriter = new TestFileWriter();
final TestIOInterface fileWriter = new TestIOInterface();
Configuration c = Configuration.load(new ByteArrayInputStream(xml.getBytes()))
.setFilenameProvider(() -> new File("z/test.dig"))
.setCircuitProvider(br::getCircuit)
.setLibraryProvider(br::getLibrary)
.setFileWriter(fileWriter);
.setIoInterface(fileWriter);
ArrayList<Command> commands = c.getCommands();
assertEquals(2, commands.size());
@ -87,12 +87,12 @@ public class ConfigurationTest extends TestCase {
ToBreakRunner br = new ToBreakRunner(new File(Resources.getRoot(), "dig/hdl/negSimple.dig"));
final TestFileWriter fileWriter = new TestFileWriter();
final TestIOInterface fileWriter = new TestIOInterface();
Configuration c = Configuration.load(new ByteArrayInputStream(xml.getBytes()))
.setFilenameProvider(() -> new File("z/test.dig"))
.setCircuitProvider(br::getCircuit)
.setLibraryProvider(br::getLibrary)
.setFileWriter(fileWriter);
.setIoInterface(fileWriter);
ArrayList<Command> commands = c.getCommands();
assertEquals(1, commands.size());
@ -105,7 +105,7 @@ public class ConfigurationTest extends TestCase {
}
private class TestFileWriter implements Configuration.FileWriter {
private class TestIOInterface implements Configuration.IOInterface {
private HashMap<String, ByteArrayOutputStream> files = new HashMap<>();
private ArrayList<StartedCommand> commands = new ArrayList<>();