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muxer is working with new template engine

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hneemann 2018-03-13 12:49:52 +01:00
parent b6e5b0ea7f
commit 70a1a8bc9d
9 changed files with 282 additions and 185 deletions
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34
src/main/java/de/neemann/digital/core/element/Keys.java
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@ -21,6 +21,9 @@ import de.neemann.gui.language.Language;
import java.awt.*;
import java.io.File;
import java.lang.reflect.Field;
import java.lang.reflect.Modifier;
import java.util.HashMap;
import java.util.Locale;
/**
@ -28,6 +31,37 @@ import java.util.Locale;
*/
public final class Keys {
private static final class InstanceHolder {
private static final HashMap<String, Key> INSTANCE = createMap();
private static HashMap<String, Key> createMap() {
HashMap<String, Key> map = new HashMap<>();
for (Field k : Keys.class.getDeclaredFields()) {
if (Modifier.isStatic(k.getModifiers()) && Key.class.isAssignableFrom(k.getType())) {
try {
Key key = (Key) k.get(null);
map.put(key.getKey(), key);
} catch (IllegalAccessException e) {
throw new RuntimeException("error accessing the Keys");
}
}
}
return map;
}
}
/**
* Returns the key of the given name.
* If key does not exist, nul is returned.
*
* @param name the name of the key
* @return the key or null
*/
public static Key getKeyByName(String name) {
return InstanceHolder.INSTANCE.get(name);
}
private Keys() {
}

1
src/main/java/de/neemann/digital/hdl/hgs/Parser.java
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@ -138,6 +138,7 @@ public class Parser {
return c -> ref.set(c, Expression.add(ref.get(c), 1));
} else if (isToken(OPEN)) {
ArrayList<Expression> args = parseArgList();
expect(SEMICOLON);
if (ref instanceof ReferenceToVar) {
return findFunctionStatement(((ReferenceToVar) ref).getName(), args);
} else

19
src/main/java/de/neemann/digital/hdl/hgs/refs/ReferenceToStruct.java
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@ -11,9 +11,6 @@ import de.neemann.digital.core.element.Keys;
import de.neemann.digital.hdl.hgs.Context;
import de.neemann.digital.hdl.hgs.EvalException;
import java.lang.reflect.Field;
import java.lang.reflect.Modifier;
import java.util.HashMap;
import java.util.Map;
/**
@ -22,20 +19,6 @@ import java.util.Map;
public class ReferenceToStruct implements Reference {
private final Reference parent;
private final String name;
private static final HashMap<String, Key> KEY_MAP = new HashMap<>();
static {
for (Field k : Keys.class.getDeclaredFields()) {
if (Modifier.isStatic(k.getModifiers()) && Key.class.isAssignableFrom(k.getType())) {
try {
Key key = (Key) k.get(null);
KEY_MAP.put(key.getKey(), key);
} catch (IllegalAccessException e) {
throw new RuntimeException("error accessing the Keys");
}
}
}
}
/**
* Creates a new struct access
@ -63,7 +46,7 @@ public class ReferenceToStruct implements Reference {
if (m instanceof Map)
return ((Map) m).get(name);
else if (m instanceof ElementAttributes) {
Key key = KEY_MAP.get(name);
Key key = Keys.getKeyByName(name);
if (key == null)
throw new EvalException("invalid key: " + name);
return ((ElementAttributes) m).get(key);

53
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
View File

@ -5,6 +5,8 @@
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Key;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.hdl.hgs.*;
import de.neemann.digital.hdl.hgs.function.FuncAdapter;
import de.neemann.digital.hdl.hgs.function.Function;
@ -20,6 +22,7 @@ import java.io.InputStreamReader;
import java.io.Reader;
import java.util.ArrayList;
import java.util.HashMap;
import java.util.List;
import static de.neemann.digital.hdl.vhdl.lib.VHDLEntitySimple.writePort;
@ -64,6 +67,21 @@ public class VHDLTemplate implements VHDLEntity {
c.setVar("portDecl", portDecl);
return null;
}
})
.addFunction("registerGeneric", new Function(1) {
@Override
public Object calcValue(Context c, ArrayList<Expression> args) throws EvalException {
List<String> generics;
if (c.contains("generics"))
generics = (List<String>) c.getVar("generics");
else {
generics = new ArrayList<>();
c.setVar("generics", generics);
}
String name = Expression.toString(args.get(0).value(c));
generics.add(name);
return null;
}
});
statements = p.parse();
staticContext = p.getStaticContext();
@ -80,7 +98,7 @@ public class VHDLTemplate implements VHDLEntity {
public void writeHeader(CodePrinter out, HDLNode node) throws IOException {
try {
Entity e = getEntity(node);
out.print(e.code);
out.print(e.getCode());
e.setWritten(true);
} catch (EvalException e) {
throw new IOException("error evaluating the template", e);
@ -126,14 +144,32 @@ public class VHDLTemplate implements VHDLEntity {
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) {
public void writeGenericMap(CodePrinter out, HDLNode node) throws HDLException, IOException {
try {
final Entity e = getEntity(node);
if (e.getGenerics() != null) {
out.println("generic map (").inc();
Separator semic = new Separator(",\n");
for (String name : e.getGenerics()) {
Key key = Keys.getKeyByName(name);
if (key != null) {
semic.check(out);
out.print(name).print(" => ").print(node.get(key).toString());
} else
throw new HDLException("unknown generic key: " + name);
}
out.println(")").dec();
}
} catch (EvalException e) {
throw new IOException("error evaluating the template", e);
}
}
@Override
public void writeGenericMap(CodePrinter out, HDLNode node) {
public void writeArchitecture(CodePrinter out, HDLNode node) {
}
@Override
public String getDescription(HDLNode node) {
return null;
@ -167,6 +203,7 @@ public class VHDLTemplate implements VHDLEntity {
private final String code;
private final String portDecl;
private final String name;
private final List<String> generics;
private boolean isWritten = false;
private Entity(HDLNode node, String name) throws EvalException {
@ -179,6 +216,10 @@ public class VHDLTemplate implements VHDLEntity {
portDecl = c.getVar("portDecl").toString();
else
portDecl = null;
if (c.contains("generics"))
generics = (List<String>) c.getVar("generics");
else
generics = null;
}
private String getCode() {
@ -200,6 +241,10 @@ public class VHDLTemplate implements VHDLEntity {
private String getName() {
return name;
}
public List<String> getGenerics() {
return generics;
}
}
private final static class FunctionType extends FuncAdapter {

17
src/main/resources/vhdl/DIG_Multiplexer.tem
View File

@ -14,18 +14,21 @@ inputs=1<<elem.'Selector Bits';
if (elem.Bits=1)
dataType=type(elem.Bits);
else
dataType="std_logic_vector ((bitCount-1) downto 0)";
dataType="std_logic_vector ((Bits-1) downto 0)";
?>
entity <?=name?> is
<? beginGenericPort()?>
<? beginGenericPort();?>
<? if (elem.Bits>1) { ?>
generic ( Bits : integer ); <? registerGeneric("Bits");?>
<? } ?>
port (
PORT_out: out <?=dataType?>;
PORT_sel: in <?=type(elem.'Selector Bits')?>;
<? for (n=0;n<inputs;n++) { ?>
PORT_in_<?=n?>: in <?=dataType if (n<inputs-1) print(";"); }?> );
<? endGenericPort()?>
<? endGenericPort();?>
end <?=name?>;
architecture <?=name?>_arch of <?=name?> is
@ -34,6 +37,10 @@ begin
PORT_out <=
<? for (n=0;n<inputs;n++) { ?>
PORT_in_<?=n?> when <?=value(n, elem.'Selector Bits') ?>,
<? } ?>
<?=value(0, elem.Bits) ?> when others;
<? }
if (elem.Bits>1)
print("(others => '0')");
else
print(value(0, elem.Bits));
?> when others;
end <?=name?>_arch;

2
src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
View File

@ -245,7 +245,7 @@ public class ParserTest extends TestCase {
public void testFunctionAsStatement() throws IOException, ParserException, EvalException {
flag = 0;
Statement s = new Parser("a : in <? type(7) ?>;")
Statement s = new Parser("a : in <? type(7); ?>;")
.addFunction("type", new FuncAdapter() {
@Override
protected Object f(long n) {

25
src/test/java/de/neemann/digital/hdl/vhdl/TestHelper.java
View File

@ -10,6 +10,10 @@ import java.util.StringTokenizer;
public class TestHelper {
static public String removeCommentLines(String code) {
return removeCommentLines(code, false);
}
static public String removeCommentLines(String code, boolean normalizeWhiteSpace) {
StringBuilder sb = new StringBuilder();
StringTokenizer st = new StringTokenizer(code, "\n");
while (st.hasMoreTokens()) {
@ -18,10 +22,29 @@ public class TestHelper {
if (!(testLine.length() == 0 || (testLine.length() >= 2 && testLine.startsWith("--")))) {
if (sb.length() > 0)
sb.append("\n");
sb.append(line);
if (normalizeWhiteSpace)
normalizeWhiteSpaces(sb, line);
else
sb.append(line);
}
}
return sb.toString();
}
private static void normalizeWhiteSpaces(StringBuilder sb, String line) {
boolean wasBlank = true;
for (int i = 0; i < line.length(); i++) {
char c = line.charAt(i);
if (c == ' ' || c == '\t') {
wasBlank = true;
} else {
if (wasBlank) {
sb.append(' ');
wasBlank = false;
}
sb.append(c);
}
}
}
}

2
src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java
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@ -126,9 +126,9 @@ public class TestInSimulator extends TestCase {
out.close();
runGHDL(vhdlFile, tb.getTestFileWritten());
}
ProcessStarter.removeFolder(dir);
} finally {
br.close();
ProcessStarter.removeFolder(dir);
}
}

314
src/test/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerTest.java
View File

@ -20,174 +20,178 @@ public class MultiplexerTest extends TestCase {
public void testSimple() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/hdl/mux.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals("LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic;\n" +
" PORT_B: in std_logic;\n" +
" PORT_C: out std_logic;\n" +
" PORT_Sel: in std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_1\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_1\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B );\n" +
" PORT_C <= S0;\n" +
"end main_arch;\n" +
assertEquals(TestHelper.removeCommentLines(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_1 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic );\n" +
"end MUX_GATE_1;\n" +
"architecture MUX_GATE_1_arch of MUX_GATE_1 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when '0',\n" +
" PORT_in_1 when '1',\n" +
" '0' when others;\n" +
"end MUX_GATE_1_arch;", TestHelper.removeCommentLines(vhdl));
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic;\n" +
" PORT_B: in std_logic;\n" +
" PORT_C: out std_logic;\n" +
" PORT_Sel: in std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_1\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_1\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B );\n" +
" PORT_C <= S0;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_1 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic );\n" +
"end MUX_GATE_1;\n" +
"architecture MUX_GATE_1_arch of MUX_GATE_1 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when '0',\n" +
" PORT_in_1 when '1',\n" +
" '0' when others;\n" +
"end MUX_GATE_1_arch;", true), TestHelper.removeCommentLines(vhdl, true));
}
public void testSimple2() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/hdl/mux2.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals("LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic;\n" +
" PORT_B: in std_logic;\n" +
" PORT_Y: out std_logic;\n" +
" PORT_Sel: in std_logic_vector (1 downto 0);\n" +
" PORT_C: in std_logic;\n" +
" PORT_D: in std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_2\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic;\n" +
" PORT_in_2: in std_logic;\n" +
" PORT_in_3: in std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_2\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B,\n" +
" PORT_in_2 => PORT_C,\n" +
" PORT_in_3 => PORT_D );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
assertEquals(TestHelper.removeCommentLines(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_2 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic;\n" +
" PORT_in_2: in std_logic;\n" +
" PORT_in_3: in std_logic );\n" +
"end MUX_GATE_2;\n" +
"architecture MUX_GATE_2_arch of MUX_GATE_2 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when \"00\",\n" +
" PORT_in_1 when \"01\",\n" +
" PORT_in_2 when \"10\",\n" +
" PORT_in_3 when \"11\",\n" +
" '0' when others;\n" +
"end MUX_GATE_2_arch;", TestHelper.removeCommentLines(vhdl));
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic;\n" +
" PORT_B: in std_logic;\n" +
" PORT_Y: out std_logic;\n" +
" PORT_Sel: in std_logic_vector (1 downto 0);\n" +
" PORT_C: in std_logic;\n" +
" PORT_D: in std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_2\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic;\n" +
" PORT_in_2: in std_logic;\n" +
" PORT_in_3: in std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_2\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B,\n" +
" PORT_in_2 => PORT_C,\n" +
" PORT_in_3 => PORT_D );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_2 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic;\n" +
" PORT_in_1: in std_logic;\n" +
" PORT_in_2: in std_logic;\n" +
" PORT_in_3: in std_logic );\n" +
"end MUX_GATE_2;\n" +
"architecture MUX_GATE_2_arch of MUX_GATE_2 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when \"00\",\n" +
" PORT_in_1 when \"01\",\n" +
" PORT_in_2 when \"10\",\n" +
" PORT_in_3 when \"11\",\n" +
" '0' when others;\n" +
"end MUX_GATE_2_arch;", true), TestHelper.removeCommentLines(vhdl, true));
}
public void testSimple3() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/hdl/mux3.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals("LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic_vector (3 downto 0);\n" +
" PORT_B: in std_logic_vector (3 downto 0);\n" +
" PORT_Y: out std_logic_vector (3 downto 0);\n" +
" PORT_Sel: in std_logic_vector (1 downto 0);\n" +
" PORT_C: in std_logic_vector (3 downto 0);\n" +
" PORT_D: in std_logic_vector (3 downto 0) );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_BUS_2\n" +
" generic ( bitCount : integer );\n" +
" port (\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_out: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_0: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_1: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_2: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_3: in std_logic_vector ( (bitCount-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (3 downto 0);\n" +
"begin\n" +
" gate0 : MUX_GATE_BUS_2\n" +
" generic map ( bitCount => 4)\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B,\n" +
" PORT_in_2 => PORT_C,\n" +
" PORT_in_3 => PORT_D );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
assertEquals(TestHelper.removeCommentLines(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_BUS_2 is\n" +
" generic ( bitCount : integer );\n" +
" port (\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_out: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_0: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_1: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_2: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_in_3: in std_logic_vector ( (bitCount-1) downto 0) );\n" +
"end MUX_GATE_BUS_2;\n" +
"architecture MUX_GATE_BUS_2_arch of MUX_GATE_BUS_2 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when \"00\",\n" +
" PORT_in_1 when \"01\",\n" +
" PORT_in_2 when \"10\",\n" +
" PORT_in_3 when \"11\",\n" +
" (others => '0') when others;\n" +
"end MUX_GATE_BUS_2_arch;", TestHelper.removeCommentLines(vhdl));
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic_vector (3 downto 0);\n" +
" PORT_B: in std_logic_vector (3 downto 0);\n" +
" PORT_Y: out std_logic_vector (3 downto 0);\n" +
" PORT_Sel: in std_logic_vector (1 downto 0);\n" +
" PORT_C: in std_logic_vector (3 downto 0);\n" +
" PORT_D: in std_logic_vector (3 downto 0) );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_BUS_2\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_2: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_3: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (3 downto 0);\n" +
"begin\n" +
" gate0 : MUX_GATE_BUS_2\n" +
" generic map (\n" +
" Bits => 4)\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_sel => PORT_Sel,\n" +
" PORT_in_0 => PORT_A,\n" +
" PORT_in_1 => PORT_B,\n" +
" PORT_in_2 => PORT_C,\n" +
" PORT_in_3 => PORT_D );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_BUS_2 is\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in_0: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_2: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in_3: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end MUX_GATE_BUS_2;\n" +
"architecture MUX_GATE_BUS_2_arch of MUX_GATE_BUS_2 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in_0 when \"00\",\n" +
" PORT_in_1 when \"01\",\n" +
" PORT_in_2 when \"10\",\n" +
" PORT_in_3 when \"11\",\n" +
" (others => '0') when others;\n" +
"end MUX_GATE_BUS_2_arch;", true), TestHelper.removeCommentLines(vhdl, true));
}
}