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fixed a bug in the D-FF vhdl template.

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This commit is contained in:
hneemann 2019-01-26 12:40:27 +01:00
parent 75be882846
commit 712e21ec31
8 changed files with 298 additions and 14 deletions
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12
src/main/resources/vhdl2/DIG_D_FF.tem
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@ -3,11 +3,17 @@ USE ieee.std_logic_1164.all;
<? <?
if (elem.Bits=1) if (elem.Bits=1)
entityName:="DIG_D_FF"; entityName:="DIG_D_FF";
else else {
entityName:="DIG_D_FF_BUS"; entityName:="DIG_D_FF_BUS";
print("use ieee.numeric_std.all;");
}
?> ?>
entity <?=entityName?> is entity <?=entityName?> is
<?if (elem.Bits>1) {?>generic ( Bits: integer );<? vhdl.registerGeneric("Bits"); }?> generic (<?if (elem.Bits>1) {?>
Default: integer; <? vhdl.registerGeneric("Default");?>
Bits: integer );<? vhdl.registerGeneric("Bits"); }
else {?>
Default: std_logic ); <? vhdl.registerGeneric("Default", "std_logic");}?>
port ( D : in <?= vhdl.genericType(elem.Bits)?>; port ( D : in <?= vhdl.genericType(elem.Bits)?>;
C : in std_logic; C : in std_logic;
Q : out <?= vhdl.genericType(elem.Bits)?>; Q : out <?= vhdl.genericType(elem.Bits)?>;
@ -15,7 +21,7 @@ entity <?=entityName?> is
end <?=entityName?>; end <?=entityName?>;
architecture Behavioral of <?=entityName?> is architecture Behavioral of <?=entityName?> is
signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>; signal state : <?= vhdl.genericType(elem.Bits)?> := <?if (elem.Bits>1) {?>std_logic_vector(to_unsigned(Default, Bits))<?} else {?>Default<? }?>;
begin begin
Q <= state; Q <= state;
notQ <= NOT( state ); notQ <= NOT( state );

2
src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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@ -45,7 +45,7 @@ public class VerilogSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try { try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples); int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
assertEquals(35, tested); assertEquals(37, tested);
assertEquals(tested+2, testBenches); assertEquals(tested+2, testBenches);
} catch (FileScanner.SkipAllException e) { } catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok // if iverilog is not installed its also ok

14
src/test/java/de/neemann/digital/hdl/vhdl2/ClockTest.java
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@ -66,7 +66,8 @@ public class ClockTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" + "USE ieee.std_logic_1164.all;\n" +
"\n" + "\n" +
"entity DIG_D_FF is\n" + "entity DIG_D_FF is\n" +
" \n" + " generic (\n" +
" Default: std_logic ); \n" +
" port ( D : in std_logic;\n" + " port ( D : in std_logic;\n" +
" C : in std_logic;\n" + " C : in std_logic;\n" +
" Q : out std_logic;\n" + " Q : out std_logic;\n" +
@ -74,7 +75,7 @@ public class ClockTest extends TestCase {
"end DIG_D_FF;\n" + "end DIG_D_FF;\n" +
"\n" + "\n" +
"architecture Behavioral of DIG_D_FF is\n" + "architecture Behavioral of DIG_D_FF is\n" +
" signal state : std_logic := '0';\n" + " signal state : std_logic := Default;\n" +
"begin\n" + "begin\n" +
" Q <= state;\n" + " Q <= state;\n" +
" notQ <= NOT( state );\n" + " notQ <= NOT( state );\n" +
@ -109,6 +110,8 @@ public class ClockTest extends TestCase {
" cin => C,\n" + " cin => C,\n" +
" cout => s0);\n" + " cout => s0);\n" +
" gate1: entity work.DIG_D_FF\n" + " gate1: entity work.DIG_D_FF\n" +
" generic map (\n" +
" Default => '0')\n" +
" port map (\n" + " port map (\n" +
" D => A,\n" + " D => A,\n" +
" C => s0,\n" + " C => s0,\n" +
@ -229,7 +232,8 @@ public class ClockTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" + "USE ieee.std_logic_1164.all;\n" +
"\n" + "\n" +
"entity DIG_D_FF is\n" + "entity DIG_D_FF is\n" +
" \n" + " generic (\n" +
" Default: std_logic ); \n" +
" port ( D : in std_logic;\n" + " port ( D : in std_logic;\n" +
" C : in std_logic;\n" + " C : in std_logic;\n" +
" Q : out std_logic;\n" + " Q : out std_logic;\n" +
@ -237,7 +241,7 @@ public class ClockTest extends TestCase {
"end DIG_D_FF;\n" + "end DIG_D_FF;\n" +
"\n" + "\n" +
"architecture Behavioral of DIG_D_FF is\n" + "architecture Behavioral of DIG_D_FF is\n" +
" signal state : std_logic := '0';\n" + " signal state : std_logic := Default;\n" +
"begin\n" + "begin\n" +
" Q <= state;\n" + " Q <= state;\n" +
" notQ <= NOT( state );\n" + " notQ <= NOT( state );\n" +
@ -276,6 +280,8 @@ public class ClockTest extends TestCase {
" cin => C,\n" + " cin => C,\n" +
" cout => s0);\n" + " cout => s0);\n" +
" gate1: entity work.DIG_D_FF\n" + " gate1: entity work.DIG_D_FF\n" +
" generic map (\n" +
" Default => '0')\n" +
" port map (\n" + " port map (\n" +
" D => A,\n" + " D => A,\n" +
" C => s0,\n" + " C => s0,\n" +

9
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
View File

@ -28,7 +28,8 @@ public class VHDLGeneratorTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" + "USE ieee.std_logic_1164.all;\n" +
"\n" + "\n" +
"entity DIG_D_FF is\n" + "entity DIG_D_FF is\n" +
" \n" + " generic (\n" +
" Default: std_logic ); \n" +
" port ( D : in std_logic;\n" + " port ( D : in std_logic;\n" +
" C : in std_logic;\n" + " C : in std_logic;\n" +
" Q : out std_logic;\n" + " Q : out std_logic;\n" +
@ -36,7 +37,7 @@ public class VHDLGeneratorTest extends TestCase {
"end DIG_D_FF;\n" + "end DIG_D_FF;\n" +
"\n" + "\n" +
"architecture Behavioral of DIG_D_FF is\n" + "architecture Behavioral of DIG_D_FF is\n" +
" signal state : std_logic := '0';\n" + " signal state : std_logic := Default;\n" +
"begin\n" + "begin\n" +
" Q <= state;\n" + " Q <= state;\n" +
" notQ <= NOT( state );\n" + " notQ <= NOT( state );\n" +
@ -71,9 +72,11 @@ public class VHDLGeneratorTest extends TestCase {
" signal Z_temp: std_logic;\n" + " signal Z_temp: std_logic;\n" +
"begin\n" + "begin\n" +
" Y_temp <= (B OR NOT C);\n" + " Y_temp <= (B OR NOT C);\n" +
" Z_temp <= NOT A;\n"+ " Z_temp <= NOT A;\n" +
" s0 <= ((A OR C) AND (Z_temp OR C) AND '1' AND NOT (B OR C) AND Y_temp);\n" + " s0 <= ((A OR C) AND (Z_temp OR C) AND '1' AND NOT (B OR C) AND Y_temp);\n" +
" gate0: entity work.DIG_D_FF\n" + " gate0: entity work.DIG_D_FF\n" +
" generic map (\n" +
" Default => '0')\n" +
" port map (\n" + " port map (\n" +
" D => s0,\n" + " D => s0,\n" +
" C => '1',\n" + " C => '1',\n" +

2
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
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@ -47,7 +47,7 @@ public class VHDLSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try { try {
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples); int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
assertEquals(35, tested); assertEquals(37, tested);
assertEquals(tested+2, testBenches); assertEquals(tested+2, testBenches);
} catch (FileScanner.SkipAllException e) { } catch (FileScanner.SkipAllException e) {
// if ghdl is not installed its also ok // if ghdl is not installed its also ok

4
src/test/java/de/neemann/digital/integration/TestExamples.java
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@ -43,8 +43,8 @@ public class TestExamples extends TestCase {
*/ */
public void testTestExamples() throws Exception { public void testTestExamples() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test"); File examples = new File(Resources.getRoot(), "/dig/test");
assertEquals(148, new FileScanner(this::check).scan(examples)); assertEquals(150, new FileScanner(this::check).scan(examples));
assertEquals(140, testCasesInFiles); assertEquals(142, testCasesInFiles);
} }
/** /**

119
src/test/resources/dig/test/vhdl/D-Default.dig Normal file
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@ -0,0 +1,119 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>VDD</elementName>
<elementAttributes/>
<pos x="340" y="180"/>
</visualElement>
<visualElement>
<elementName>VDD</elementName>
<elementAttributes/>
<pos x="340" y="280"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>C</string>
</entry>
</elementAttributes>
<pos x="320" y="320"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Q1</string>
</entry>
</elementAttributes>
<pos x="460" y="200"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Q2</string>
</entry>
</elementAttributes>
<pos x="460" y="300"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>C Q1 Q2
0 0 1
C 1 1
</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="220" y="180"/>
</visualElement>
<visualElement>
<elementName>D_FF</elementName>
<elementAttributes/>
<pos x="380" y="200"/>
</visualElement>
<visualElement>
<elementName>D_FF</elementName>
<elementAttributes>
<entry>
<string>Default</string>
<int>1</int>
</entry>
</elementAttributes>
<pos x="380" y="300"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="320" y="320"/>
<p2 x="360" y="320"/>
</wire>
<wire>
<p1 x="360" y="320"/>
<p2 x="380" y="320"/>
</wire>
<wire>
<p1 x="340" y="200"/>
<p2 x="380" y="200"/>
</wire>
<wire>
<p1 x="440" y="200"/>
<p2 x="460" y="200"/>
</wire>
<wire>
<p1 x="360" y="220"/>
<p2 x="380" y="220"/>
</wire>
<wire>
<p1 x="340" y="300"/>
<p2 x="380" y="300"/>
</wire>
<wire>
<p1 x="440" y="300"/>
<p2 x="460" y="300"/>
</wire>
<wire>
<p1 x="340" y="180"/>
<p2 x="340" y="200"/>
</wire>
<wire>
<p1 x="340" y="280"/>
<p2 x="340" y="300"/>
</wire>
<wire>
<p1 x="360" y="220"/>
<p2 x="360" y="320"/>
</wire>
</wires>
</circuit>

150
src/test/resources/dig/test/vhdl/D-DefaultBus.dig Normal file
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@ -0,0 +1,150 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>VDD</elementName>
<elementAttributes>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="340" y="180"/>
</visualElement>
<visualElement>
<elementName>VDD</elementName>
<elementAttributes>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="340" y="280"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>C</string>
</entry>
</elementAttributes>
<pos x="320" y="320"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Q1</string>
</entry>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="460" y="200"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Q2</string>
</entry>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="460" y="300"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>C Q1 Q2
0 5 0xA
C 0xf 0xf
</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="220" y="180"/>
</visualElement>
<visualElement>
<elementName>D_FF</elementName>
<elementAttributes>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
<entry>
<string>Default</string>
<int>5</int>
</entry>
</elementAttributes>
<pos x="380" y="200"/>
</visualElement>
<visualElement>
<elementName>D_FF</elementName>
<elementAttributes>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
<entry>
<string>Default</string>
<int>10</int>
</entry>
</elementAttributes>
<pos x="380" y="300"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="320" y="320"/>
<p2 x="360" y="320"/>
</wire>
<wire>
<p1 x="360" y="320"/>
<p2 x="380" y="320"/>
</wire>
<wire>
<p1 x="340" y="200"/>
<p2 x="380" y="200"/>
</wire>
<wire>
<p1 x="440" y="200"/>
<p2 x="460" y="200"/>
</wire>
<wire>
<p1 x="360" y="220"/>
<p2 x="380" y="220"/>
</wire>
<wire>
<p1 x="340" y="300"/>
<p2 x="380" y="300"/>
</wire>
<wire>
<p1 x="440" y="300"/>
<p2 x="460" y="300"/>
</wire>
<wire>
<p1 x="340" y="180"/>
<p2 x="340" y="200"/>
</wire>
<wire>
<p1 x="340" y="280"/>
<p2 x="340" y="300"/>
</wire>
<wire>
<p1 x="360" y="220"/>
<p2 x="360" y="320"/>
</wire>
</wires>
</circuit>