mirror of
https://github.com/hneemann/Digital.git
synced 2025-09-16 16:34:47 -04:00
fixed a bug in the D-FF vhdl template.
This commit is contained in:
hneemann
parent
75be882846
commit
712e21ec31
@ -3,11 +3,17 @@ USE ieee.std_logic_1164.all;
|
||||
<?
|
||||
if (elem.Bits=1)
|
||||
entityName:="DIG_D_FF";
|
||||
else
|
||||
else {
|
||||
entityName:="DIG_D_FF_BUS";
|
||||
print("use ieee.numeric_std.all;");
|
||||
}
|
||||
?>
|
||||
entity <?=entityName?> is
|
||||
<?if (elem.Bits>1) {?>generic ( Bits: integer );<? vhdl.registerGeneric("Bits"); }?>
|
||||
generic (<?if (elem.Bits>1) {?>
|
||||
Default: integer; <? vhdl.registerGeneric("Default");?>
|
||||
Bits: integer );<? vhdl.registerGeneric("Bits"); }
|
||||
else {?>
|
||||
Default: std_logic ); <? vhdl.registerGeneric("Default", "std_logic");}?>
|
||||
port ( D : in <?= vhdl.genericType(elem.Bits)?>;
|
||||
C : in std_logic;
|
||||
Q : out <?= vhdl.genericType(elem.Bits)?>;
|
||||
@ -15,7 +21,7 @@ entity <?=entityName?> is
|
||||
end <?=entityName?>;
|
||||
|
||||
architecture Behavioral of <?=entityName?> is
|
||||
signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
|
||||
signal state : <?= vhdl.genericType(elem.Bits)?> := <?if (elem.Bits>1) {?>std_logic_vector(to_unsigned(Default, Bits))<?} else {?>Default<? }?>;
|
||||
begin
|
||||
Q <= state;
|
||||
notQ <= NOT( state );
|
||||
|
||||
@ -45,7 +45,7 @@ public class VerilogSimulatorTest extends TestCase {
|
||||
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
|
||||
try {
|
||||
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
|
||||
assertEquals(35, tested);
|
||||
assertEquals(37, tested);
|
||||
assertEquals(tested+2, testBenches);
|
||||
} catch (FileScanner.SkipAllException e) {
|
||||
// if iverilog is not installed its also ok
|
||||
|
||||
@ -66,7 +66,8 @@ public class ClockTest extends TestCase {
|
||||
"USE ieee.std_logic_1164.all;\n" +
|
||||
"\n" +
|
||||
"entity DIG_D_FF is\n" +
|
||||
" \n" +
|
||||
" generic (\n" +
|
||||
" Default: std_logic ); \n" +
|
||||
" port ( D : in std_logic;\n" +
|
||||
" C : in std_logic;\n" +
|
||||
" Q : out std_logic;\n" +
|
||||
@ -74,7 +75,7 @@ public class ClockTest extends TestCase {
|
||||
"end DIG_D_FF;\n" +
|
||||
"\n" +
|
||||
"architecture Behavioral of DIG_D_FF is\n" +
|
||||
" signal state : std_logic := '0';\n" +
|
||||
" signal state : std_logic := Default;\n" +
|
||||
"begin\n" +
|
||||
" Q <= state;\n" +
|
||||
" notQ <= NOT( state );\n" +
|
||||
@ -109,6 +110,8 @@ public class ClockTest extends TestCase {
|
||||
" cin => C,\n" +
|
||||
" cout => s0);\n" +
|
||||
" gate1: entity work.DIG_D_FF\n" +
|
||||
" generic map (\n" +
|
||||
" Default => '0')\n" +
|
||||
" port map (\n" +
|
||||
" D => A,\n" +
|
||||
" C => s0,\n" +
|
||||
@ -229,7 +232,8 @@ public class ClockTest extends TestCase {
|
||||
"USE ieee.std_logic_1164.all;\n" +
|
||||
"\n" +
|
||||
"entity DIG_D_FF is\n" +
|
||||
" \n" +
|
||||
" generic (\n" +
|
||||
" Default: std_logic ); \n" +
|
||||
" port ( D : in std_logic;\n" +
|
||||
" C : in std_logic;\n" +
|
||||
" Q : out std_logic;\n" +
|
||||
@ -237,7 +241,7 @@ public class ClockTest extends TestCase {
|
||||
"end DIG_D_FF;\n" +
|
||||
"\n" +
|
||||
"architecture Behavioral of DIG_D_FF is\n" +
|
||||
" signal state : std_logic := '0';\n" +
|
||||
" signal state : std_logic := Default;\n" +
|
||||
"begin\n" +
|
||||
" Q <= state;\n" +
|
||||
" notQ <= NOT( state );\n" +
|
||||
@ -276,6 +280,8 @@ public class ClockTest extends TestCase {
|
||||
" cin => C,\n" +
|
||||
" cout => s0);\n" +
|
||||
" gate1: entity work.DIG_D_FF\n" +
|
||||
" generic map (\n" +
|
||||
" Default => '0')\n" +
|
||||
" port map (\n" +
|
||||
" D => A,\n" +
|
||||
" C => s0,\n" +
|
||||
|
||||
@ -28,7 +28,8 @@ public class VHDLGeneratorTest extends TestCase {
|
||||
"USE ieee.std_logic_1164.all;\n" +
|
||||
"\n" +
|
||||
"entity DIG_D_FF is\n" +
|
||||
" \n" +
|
||||
" generic (\n" +
|
||||
" Default: std_logic ); \n" +
|
||||
" port ( D : in std_logic;\n" +
|
||||
" C : in std_logic;\n" +
|
||||
" Q : out std_logic;\n" +
|
||||
@ -36,7 +37,7 @@ public class VHDLGeneratorTest extends TestCase {
|
||||
"end DIG_D_FF;\n" +
|
||||
"\n" +
|
||||
"architecture Behavioral of DIG_D_FF is\n" +
|
||||
" signal state : std_logic := '0';\n" +
|
||||
" signal state : std_logic := Default;\n" +
|
||||
"begin\n" +
|
||||
" Q <= state;\n" +
|
||||
" notQ <= NOT( state );\n" +
|
||||
@ -71,9 +72,11 @@ public class VHDLGeneratorTest extends TestCase {
|
||||
" signal Z_temp: std_logic;\n" +
|
||||
"begin\n" +
|
||||
" Y_temp <= (B OR NOT C);\n" +
|
||||
" Z_temp <= NOT A;\n"+
|
||||
" Z_temp <= NOT A;\n" +
|
||||
" s0 <= ((A OR C) AND (Z_temp OR C) AND '1' AND NOT (B OR C) AND Y_temp);\n" +
|
||||
" gate0: entity work.DIG_D_FF\n" +
|
||||
" generic map (\n" +
|
||||
" Default => '0')\n" +
|
||||
" port map (\n" +
|
||||
" D => s0,\n" +
|
||||
" C => '1',\n" +
|
||||
|
||||
@ -47,7 +47,7 @@ public class VHDLSimulatorTest extends TestCase {
|
||||
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
|
||||
try {
|
||||
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
|
||||
assertEquals(35, tested);
|
||||
assertEquals(37, tested);
|
||||
assertEquals(tested+2, testBenches);
|
||||
} catch (FileScanner.SkipAllException e) {
|
||||
// if ghdl is not installed its also ok
|
||||
|
||||
@ -43,8 +43,8 @@ public class TestExamples extends TestCase {
|
||||
*/
|
||||
public void testTestExamples() throws Exception {
|
||||
File examples = new File(Resources.getRoot(), "/dig/test");
|
||||
assertEquals(148, new FileScanner(this::check).scan(examples));
|
||||
assertEquals(140, testCasesInFiles);
|
||||
assertEquals(150, new FileScanner(this::check).scan(examples));
|
||||
assertEquals(142, testCasesInFiles);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
119
src/test/resources/dig/test/vhdl/D-Default.dig
Normal file
119
src/test/resources/dig/test/vhdl/D-Default.dig
Normal file
@ -0,0 +1,119 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<circuit>
|
||||
<version>1</version>
|
||||
<attributes/>
|
||||
<visualElements>
|
||||
<visualElement>
|
||||
<elementName>VDD</elementName>
|
||||
<elementAttributes/>
|
||||
<pos x="340" y="180"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>VDD</elementName>
|
||||
<elementAttributes/>
|
||||
<pos x="340" y="280"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>In</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>C</string>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="320" y="320"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Out</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>Q1</string>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="460" y="200"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Out</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>Q2</string>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="460" y="300"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Testcase</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Testdata</string>
|
||||
<testData>
|
||||
<dataString>C Q1 Q2
|
||||
0 0 1
|
||||
C 1 1
|
||||
</dataString>
|
||||
</testData>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="220" y="180"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>D_FF</elementName>
|
||||
<elementAttributes/>
|
||||
<pos x="380" y="200"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>D_FF</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Default</string>
|
||||
<int>1</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="380" y="300"/>
|
||||
</visualElement>
|
||||
</visualElements>
|
||||
<wires>
|
||||
<wire>
|
||||
<p1 x="320" y="320"/>
|
||||
<p2 x="360" y="320"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="320"/>
|
||||
<p2 x="380" y="320"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="200"/>
|
||||
<p2 x="380" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="440" y="200"/>
|
||||
<p2 x="460" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="220"/>
|
||||
<p2 x="380" y="220"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="300"/>
|
||||
<p2 x="380" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="440" y="300"/>
|
||||
<p2 x="460" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="180"/>
|
||||
<p2 x="340" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="280"/>
|
||||
<p2 x="340" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="220"/>
|
||||
<p2 x="360" y="320"/>
|
||||
</wire>
|
||||
</wires>
|
||||
</circuit>
|
||||
150
src/test/resources/dig/test/vhdl/D-DefaultBus.dig
Normal file
150
src/test/resources/dig/test/vhdl/D-DefaultBus.dig
Normal file
@ -0,0 +1,150 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<circuit>
|
||||
<version>1</version>
|
||||
<attributes/>
|
||||
<visualElements>
|
||||
<visualElement>
|
||||
<elementName>VDD</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="340" y="180"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>VDD</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="340" y="280"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>In</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>C</string>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="320" y="320"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Out</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>Q1</string>
|
||||
</entry>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="460" y="200"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Out</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Label</string>
|
||||
<string>Q2</string>
|
||||
</entry>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="460" y="300"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>Testcase</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Testdata</string>
|
||||
<testData>
|
||||
<dataString>C Q1 Q2
|
||||
0 5 0xA
|
||||
C 0xf 0xf
|
||||
</dataString>
|
||||
</testData>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="220" y="180"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>D_FF</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
<entry>
|
||||
<string>Default</string>
|
||||
<int>5</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="380" y="200"/>
|
||||
</visualElement>
|
||||
<visualElement>
|
||||
<elementName>D_FF</elementName>
|
||||
<elementAttributes>
|
||||
<entry>
|
||||
<string>Bits</string>
|
||||
<int>4</int>
|
||||
</entry>
|
||||
<entry>
|
||||
<string>Default</string>
|
||||
<int>10</int>
|
||||
</entry>
|
||||
</elementAttributes>
|
||||
<pos x="380" y="300"/>
|
||||
</visualElement>
|
||||
</visualElements>
|
||||
<wires>
|
||||
<wire>
|
||||
<p1 x="320" y="320"/>
|
||||
<p2 x="360" y="320"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="320"/>
|
||||
<p2 x="380" y="320"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="200"/>
|
||||
<p2 x="380" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="440" y="200"/>
|
||||
<p2 x="460" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="220"/>
|
||||
<p2 x="380" y="220"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="300"/>
|
||||
<p2 x="380" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="440" y="300"/>
|
||||
<p2 x="460" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="180"/>
|
||||
<p2 x="340" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="280"/>
|
||||
<p2 x="340" y="300"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="360" y="220"/>
|
||||
<p2 x="360" y="320"/>
|
||||
</wire>
|
||||
</wires>
|
||||
</circuit>
|
||||
Loading…
x
Reference in New Issue
Block a user