mirror of
https://github.com/hneemann/Digital.git
synced 2025-09-16 08:25:09 -04:00
fixed a bug in the D-FF vhdl template.
This commit is contained in:
hneemann
parent
75be882846
commit
712e21ec31
@ -3,11 +3,17 @@ USE ieee.std_logic_1164.all;
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<?
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if (elem.Bits=1)
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entityName:="DIG_D_FF";
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else
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else {
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entityName:="DIG_D_FF_BUS";
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print("use ieee.numeric_std.all;");
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}
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?>
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entity <?=entityName?> is
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<?if (elem.Bits>1) {?>generic ( Bits: integer );<? vhdl.registerGeneric("Bits"); }?>
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generic (<?if (elem.Bits>1) {?>
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Default: integer; <? vhdl.registerGeneric("Default");?>
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Bits: integer );<? vhdl.registerGeneric("Bits"); }
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else {?>
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Default: std_logic ); <? vhdl.registerGeneric("Default", "std_logic");}?>
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port ( D : in <?= vhdl.genericType(elem.Bits)?>;
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C : in std_logic;
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Q : out <?= vhdl.genericType(elem.Bits)?>;
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@ -15,7 +21,7 @@ entity <?=entityName?> is
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end <?=entityName?>;
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architecture Behavioral of <?=entityName?> is
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signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
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signal state : <?= vhdl.genericType(elem.Bits)?> := <?if (elem.Bits>1) {?>std_logic_vector(to_unsigned(Default, Bits))<?} else {?>Default<? }?>;
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begin
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Q <= state;
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notQ <= NOT( state );
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@ -45,7 +45,7 @@ public class VerilogSimulatorTest extends TestCase {
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File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
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try {
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int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
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assertEquals(35, tested);
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assertEquals(37, tested);
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assertEquals(tested+2, testBenches);
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} catch (FileScanner.SkipAllException e) {
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// if iverilog is not installed its also ok
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@ -66,7 +66,8 @@ public class ClockTest extends TestCase {
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"USE ieee.std_logic_1164.all;\n" +
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"\n" +
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"entity DIG_D_FF is\n" +
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" \n" +
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" generic (\n" +
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" Default: std_logic ); \n" +
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" port ( D : in std_logic;\n" +
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" C : in std_logic;\n" +
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" Q : out std_logic;\n" +
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@ -74,7 +75,7 @@ public class ClockTest extends TestCase {
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"end DIG_D_FF;\n" +
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"\n" +
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"architecture Behavioral of DIG_D_FF is\n" +
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" signal state : std_logic := '0';\n" +
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" signal state : std_logic := Default;\n" +
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"begin\n" +
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" Q <= state;\n" +
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" notQ <= NOT( state );\n" +
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@ -109,6 +110,8 @@ public class ClockTest extends TestCase {
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" cin => C,\n" +
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" cout => s0);\n" +
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" gate1: entity work.DIG_D_FF\n" +
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" generic map (\n" +
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" Default => '0')\n" +
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" port map (\n" +
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" D => A,\n" +
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" C => s0,\n" +
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@ -229,7 +232,8 @@ public class ClockTest extends TestCase {
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"USE ieee.std_logic_1164.all;\n" +
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"\n" +
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"entity DIG_D_FF is\n" +
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" \n" +
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" generic (\n" +
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" Default: std_logic ); \n" +
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" port ( D : in std_logic;\n" +
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" C : in std_logic;\n" +
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" Q : out std_logic;\n" +
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@ -237,7 +241,7 @@ public class ClockTest extends TestCase {
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"end DIG_D_FF;\n" +
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"\n" +
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"architecture Behavioral of DIG_D_FF is\n" +
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" signal state : std_logic := '0';\n" +
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" signal state : std_logic := Default;\n" +
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"begin\n" +
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" Q <= state;\n" +
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" notQ <= NOT( state );\n" +
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@ -276,6 +280,8 @@ public class ClockTest extends TestCase {
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" cin => C,\n" +
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" cout => s0);\n" +
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" gate1: entity work.DIG_D_FF\n" +
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" generic map (\n" +
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" Default => '0')\n" +
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" port map (\n" +
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" D => A,\n" +
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" C => s0,\n" +
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@ -28,7 +28,8 @@ public class VHDLGeneratorTest extends TestCase {
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"USE ieee.std_logic_1164.all;\n" +
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"\n" +
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"entity DIG_D_FF is\n" +
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" \n" +
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" generic (\n" +
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" Default: std_logic ); \n" +
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" port ( D : in std_logic;\n" +
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" C : in std_logic;\n" +
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" Q : out std_logic;\n" +
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@ -36,7 +37,7 @@ public class VHDLGeneratorTest extends TestCase {
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"end DIG_D_FF;\n" +
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"\n" +
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"architecture Behavioral of DIG_D_FF is\n" +
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" signal state : std_logic := '0';\n" +
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" signal state : std_logic := Default;\n" +
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"begin\n" +
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" Q <= state;\n" +
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" notQ <= NOT( state );\n" +
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@ -71,9 +72,11 @@ public class VHDLGeneratorTest extends TestCase {
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" signal Z_temp: std_logic;\n" +
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"begin\n" +
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" Y_temp <= (B OR NOT C);\n" +
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" Z_temp <= NOT A;\n"+
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" Z_temp <= NOT A;\n" +
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" s0 <= ((A OR C) AND (Z_temp OR C) AND '1' AND NOT (B OR C) AND Y_temp);\n" +
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" gate0: entity work.DIG_D_FF\n" +
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" generic map (\n" +
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" Default => '0')\n" +
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" port map (\n" +
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" D => s0,\n" +
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" C => '1',\n" +
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@ -47,7 +47,7 @@ public class VHDLSimulatorTest extends TestCase {
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File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
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try {
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int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
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assertEquals(35, tested);
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assertEquals(37, tested);
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assertEquals(tested+2, testBenches);
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} catch (FileScanner.SkipAllException e) {
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// if ghdl is not installed its also ok
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@ -43,8 +43,8 @@ public class TestExamples extends TestCase {
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*/
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public void testTestExamples() throws Exception {
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File examples = new File(Resources.getRoot(), "/dig/test");
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assertEquals(148, new FileScanner(this::check).scan(examples));
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assertEquals(140, testCasesInFiles);
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assertEquals(150, new FileScanner(this::check).scan(examples));
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assertEquals(142, testCasesInFiles);
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}
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/**
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119
src/test/resources/dig/test/vhdl/D-Default.dig
Normal file
119
src/test/resources/dig/test/vhdl/D-Default.dig
Normal file
@ -0,0 +1,119 @@
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<?xml version="1.0" encoding="utf-8"?>
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<circuit>
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<version>1</version>
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<attributes/>
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<visualElements>
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<visualElement>
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<elementName>VDD</elementName>
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<elementAttributes/>
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<pos x="340" y="180"/>
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</visualElement>
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<visualElement>
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<elementName>VDD</elementName>
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<elementAttributes/>
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<pos x="340" y="280"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>C</string>
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</entry>
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</elementAttributes>
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<pos x="320" y="320"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q1</string>
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</entry>
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</elementAttributes>
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<pos x="460" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q2</string>
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</entry>
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</elementAttributes>
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<pos x="460" y="300"/>
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</visualElement>
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<visualElement>
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<elementName>Testcase</elementName>
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<elementAttributes>
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<entry>
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<string>Testdata</string>
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<testData>
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<dataString>C Q1 Q2
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0 0 1
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C 1 1
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</dataString>
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</testData>
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</entry>
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</elementAttributes>
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<pos x="220" y="180"/>
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</visualElement>
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<visualElement>
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<elementName>D_FF</elementName>
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<elementAttributes/>
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<pos x="380" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>D_FF</elementName>
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<elementAttributes>
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<entry>
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<string>Default</string>
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<int>1</int>
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</entry>
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</elementAttributes>
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<pos x="380" y="300"/>
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</visualElement>
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</visualElements>
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<wires>
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<wire>
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<p1 x="320" y="320"/>
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<p2 x="360" y="320"/>
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</wire>
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<wire>
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<p1 x="360" y="320"/>
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<p2 x="380" y="320"/>
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</wire>
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<wire>
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<p1 x="340" y="200"/>
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<p2 x="380" y="200"/>
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</wire>
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<wire>
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<p1 x="440" y="200"/>
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<p2 x="460" y="200"/>
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</wire>
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<wire>
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<p1 x="360" y="220"/>
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<p2 x="380" y="220"/>
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</wire>
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<wire>
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<p1 x="340" y="300"/>
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<p2 x="380" y="300"/>
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</wire>
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<wire>
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<p1 x="440" y="300"/>
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<p2 x="460" y="300"/>
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</wire>
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<wire>
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<p1 x="340" y="180"/>
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<p2 x="340" y="200"/>
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</wire>
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<wire>
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<p1 x="340" y="280"/>
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<p2 x="340" y="300"/>
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</wire>
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<wire>
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<p1 x="360" y="220"/>
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<p2 x="360" y="320"/>
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</wire>
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</wires>
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</circuit>
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150
src/test/resources/dig/test/vhdl/D-DefaultBus.dig
Normal file
150
src/test/resources/dig/test/vhdl/D-DefaultBus.dig
Normal file
@ -0,0 +1,150 @@
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<?xml version="1.0" encoding="utf-8"?>
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<circuit>
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<version>1</version>
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<attributes/>
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<visualElements>
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<visualElement>
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<elementName>VDD</elementName>
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<elementAttributes>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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</elementAttributes>
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<pos x="340" y="180"/>
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</visualElement>
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<visualElement>
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<elementName>VDD</elementName>
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<elementAttributes>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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</elementAttributes>
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<pos x="340" y="280"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>C</string>
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</entry>
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</elementAttributes>
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<pos x="320" y="320"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q1</string>
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</entry>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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</elementAttributes>
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<pos x="460" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q2</string>
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</entry>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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</elementAttributes>
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<pos x="460" y="300"/>
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</visualElement>
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<visualElement>
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<elementName>Testcase</elementName>
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<elementAttributes>
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<entry>
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<string>Testdata</string>
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<testData>
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<dataString>C Q1 Q2
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0 5 0xA
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C 0xf 0xf
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</dataString>
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</testData>
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</entry>
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</elementAttributes>
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<pos x="220" y="180"/>
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</visualElement>
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<visualElement>
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<elementName>D_FF</elementName>
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<elementAttributes>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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<entry>
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<string>Default</string>
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<int>5</int>
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</entry>
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</elementAttributes>
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<pos x="380" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>D_FF</elementName>
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<elementAttributes>
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<entry>
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<string>Bits</string>
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<int>4</int>
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</entry>
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<entry>
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<string>Default</string>
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<int>10</int>
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</entry>
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</elementAttributes>
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<pos x="380" y="300"/>
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</visualElement>
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</visualElements>
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<wires>
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<wire>
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<p1 x="320" y="320"/>
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<p2 x="360" y="320"/>
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</wire>
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<wire>
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<p1 x="360" y="320"/>
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<p2 x="380" y="320"/>
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</wire>
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<wire>
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<p1 x="340" y="200"/>
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<p2 x="380" y="200"/>
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</wire>
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<wire>
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<p1 x="440" y="200"/>
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<p2 x="460" y="200"/>
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</wire>
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<wire>
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<p1 x="360" y="220"/>
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<p2 x="380" y="220"/>
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</wire>
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<wire>
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<p1 x="340" y="300"/>
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<p2 x="380" y="300"/>
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</wire>
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<wire>
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<p1 x="440" y="300"/>
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<p2 x="460" y="300"/>
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</wire>
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<wire>
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<p1 x="340" y="180"/>
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<p2 x="340" y="200"/>
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</wire>
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<wire>
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<p1 x="340" y="280"/>
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<p2 x="340" y="300"/>
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</wire>
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<wire>
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<p1 x="360" y="220"/>
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<p2 x="360" y="320"/>
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</wire>
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</wires>
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</circuit>
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