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Fixed a problem with the generated verilog code for the ROM component

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This commit is contained in:
Ivan de Jesus Deras 2018-06-07 14:28:06 -06:00
parent 9af27c79cd
commit 922a09eef7
2 changed files with 2 additions and 4 deletions
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1
src/main/java/de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java
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@ -32,7 +32,6 @@ public class VerilogTemplate implements VerilogElement {
private final static String MODULE_PREFIX = "DIG_"; private final static String MODULE_PREFIX = "DIG_";
private final String moduleBaseName; private final String moduleBaseName;
private String moduleName;
private final Statement statements; private final Statement statements;
private HashMap<String, Module> modules; private HashMap<String, Module> modules;

5
src/main/resources/verilog/DIG_ROM.v
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@ -8,12 +8,11 @@
?>module <?= moduleName ?> ( ?>module <?= moduleName ?> (
input <?= aBitRange ?> A, input <?= aBitRange ?> A,
input sel, input sel,
output <?= dBitRange ?> D output reg <?= dBitRange ?> D
); );
reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>]; reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
reg D;
always @ (A or sel) begin always @ (*) begin
if (~sel) if (~sel)
D = <?= elem.Bits ?>'hz;<? D = <?= elem.Bits ?>'hz;<?
if (romSize < romMaxSize) { if (romSize < romMaxSize) {