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fixes #387

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hneemann 2019-11-27 19:39:11 +01:00
parent 8d1defdfe0
commit a624fb4adb
3 changed files with 14 additions and 10 deletions
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2
src/main/java/de/neemann/digital/hdl/model2/optimizations/InlineManyToOne.java
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@ -21,7 +21,7 @@ public class InlineManyToOne implements Optimization {
if (node instanceof HDLNodeAssignment) { if (node instanceof HDLNodeAssignment) {
HDLNodeAssignment assign = (HDLNodeAssignment) node; HDLNodeAssignment assign = (HDLNodeAssignment) node;
final HDLNet net = assign.getTargetNet(); final HDLNet net = assign.getTargetNet();
if (net.getInputs().size() == 1) { if (net != null && net.getInputs().size() == 1) {
HDLNode receiver = net.getInputs().get(0).getParent(); HDLNode receiver = net.getInputs().get(0).getParent();
if (receiver instanceof HDLNodeSplitterManyToOne) { if (receiver instanceof HDLNodeSplitterManyToOne) {
HDLNodeSplitterManyToOne mto = (HDLNodeSplitterManyToOne) receiver; HDLNodeSplitterManyToOne mto = (HDLNodeSplitterManyToOne) receiver;

14
src/main/java/de/neemann/digital/hdl/verilog2/VerilogCreator.java
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@ -61,7 +61,7 @@ public class VerilogCreator {
* @return the verilog signal type * @return the verilog signal type
*/ */
public static String getType(HDLPort.Direction dir, int bits) { public static String getType(HDLPort.Direction dir, int bits) {
String result = (dir == HDLPort.Direction.IN)? "input" : "output"; String result = (dir == HDLPort.Direction.IN) ? "input" : "output";
if (bits > 1) { if (bits > 1) {
result += " [" + (bits - 1) + ":0]"; result += " [" + (bits - 1) + ":0]";
@ -110,7 +110,7 @@ public class VerilogCreator {
* Prints the given circuit to the output. * Prints the given circuit to the output.
* Also all needed entities are printed. * Also all needed entities are printed.
* *
* @param circuit the circuit to print * @param circuit the circuit to print
* @param moduleName the module name * @param moduleName the module name
* @throws IOException IOException * @throws IOException IOException
* @throws HDLException HDLException * @throws HDLException HDLException
@ -244,7 +244,7 @@ public class VerilogCreator {
String instanceName = entityName.trim() + "_i" + num; String instanceName = entityName.trim() + "_i" + num;
out.print(instanceName + " ") out.print(instanceName + " ")
.println("("); .println("(");
out.inc(); out.inc();
Separator sep = new Separator(out, ",\n"); Separator sep = new Separator(out, ",\n");
@ -265,9 +265,11 @@ public class VerilogCreator {
} }
private void printExpression(HDLNodeAssignment node) throws IOException, HDLException { private void printExpression(HDLNodeAssignment node) throws IOException, HDLException {
out.print("assign ").print(node.getTargetNet().getName()).print(" = "); if (node.getTargetNet() != null) {
printExpression(node.getExpression()); out.print("assign ").print(node.getTargetNet().getName()).print(" = ");
out.println(";"); printExpression(node.getExpression());
out.println(";");
}
} }
private void printExpression(Expression expression) throws IOException, HDLException { private void printExpression(Expression expression) throws IOException, HDLException {

8
src/main/java/de/neemann/digital/hdl/vhdl2/VHDLCreator.java
View File

@ -254,9 +254,11 @@ public class VHDLCreator {
} }
private void printExpression(HDLNodeAssignment node) throws IOException, HDLException { private void printExpression(HDLNodeAssignment node) throws IOException, HDLException {
out.print(node.getTargetNet().getName()).print(" <= "); if (node.getTargetNet() != null) {
printExpression(node.getExpression()); out.print(node.getTargetNet().getName()).print(" <= ");
out.println(";"); printExpression(node.getExpression());
out.println(";");
}
} }
private void printExpression(Expression expression) throws IOException, HDLException { private void printExpression(Expression expression) throws IOException, HDLException {