This commit is contained in:
hneemann 2019-11-27 19:39:11 +01:00
parent 8d1defdfe0
commit a624fb4adb
3 changed files with 14 additions and 10 deletions

View File

@ -21,7 +21,7 @@ public class InlineManyToOne implements Optimization {
if (node instanceof HDLNodeAssignment) {
HDLNodeAssignment assign = (HDLNodeAssignment) node;
final HDLNet net = assign.getTargetNet();
if (net.getInputs().size() == 1) {
if (net != null && net.getInputs().size() == 1) {
HDLNode receiver = net.getInputs().get(0).getParent();
if (receiver instanceof HDLNodeSplitterManyToOne) {
HDLNodeSplitterManyToOne mto = (HDLNodeSplitterManyToOne) receiver;

View File

@ -61,7 +61,7 @@ public class VerilogCreator {
* @return the verilog signal type
*/
public static String getType(HDLPort.Direction dir, int bits) {
String result = (dir == HDLPort.Direction.IN)? "input" : "output";
String result = (dir == HDLPort.Direction.IN) ? "input" : "output";
if (bits > 1) {
result += " [" + (bits - 1) + ":0]";
@ -265,10 +265,12 @@ public class VerilogCreator {
}
private void printExpression(HDLNodeAssignment node) throws IOException, HDLException {
if (node.getTargetNet() != null) {
out.print("assign ").print(node.getTargetNet().getName()).print(" = ");
printExpression(node.getExpression());
out.println(";");
}
}
private void printExpression(Expression expression) throws IOException, HDLException {
if (expression instanceof ExprVar)

View File

@ -254,10 +254,12 @@ public class VHDLCreator {
}
private void printExpression(HDLNodeAssignment node) throws IOException, HDLException {
if (node.getTargetNet() != null) {
out.print(node.getTargetNet().getName()).print(" <= ");
printExpression(node.getExpression());
out.println(";");
}
}
private void printExpression(Expression expression) throws IOException, HDLException {
if (expression instanceof ExprVar)