mirror of
https://github.com/hneemann/Digital.git
synced 2025-09-12 06:15:32 -04:00
Merge branch 'Chinese'
This commit is contained in:
hneemann
commit
b9dd35a7bc
@ -76,13 +76,15 @@ All other tests, including the HDL tests, were executed without errors.
|
||||
|
||||
## Documentation ##
|
||||
|
||||
The [documentation](https://github.com/hneemann/Digital/releases/latest) is available in English, German, Spanish and Portuguese.
|
||||
The [documentation](https://github.com/hneemann/Digital/releases/latest) is available in English,
|
||||
German, Spanish, Portuguese and simplified Chinese.
|
||||
It is still very incomplete but it contains a chapter "First Steps" which explains the basic usage of Digital.
|
||||
The documentation also contains a list of available 74xx chips and a list of available keyboard shortcuts.
|
||||
|
||||
## Translations ##
|
||||
|
||||
So far Digital is available in English, German, Spanish and Portuguese. If someone wants to add a
|
||||
So far Digital is available in English, German, Spanish, Portuguese and simplified Chinese.
|
||||
If someone wants to add a
|
||||
new translation, please let me [know](mailto:digital-simulator@web.de).
|
||||
I can provide you with a special file for translation. This file is much easier to
|
||||
translate than the [files](https://github.com/hneemann/Digital/blob/master/src/main/resources/lang)
|
||||
@ -269,6 +271,7 @@ Many thanks to the following persons for their help:
|
||||
has provided the Portuguese translation.
|
||||
* Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain
|
||||
has provided the Spanish translation.
|
||||
* XinJun Ma ([@itviewer](https://github.com/itviewer)) has provided the Chinese translation.
|
||||
|
||||
## Additional Screenshots
|
||||
|
||||
|
||||
@ -23,4 +23,5 @@ modified keys.
|
||||
<lang name="de">Deutsch</lang>
|
||||
<lang name="es">Español</lang>
|
||||
<lang name="pt">Português</lang>
|
||||
<lang name="zh">简体中文</lang>
|
||||
</languages>
|
||||
|
||||
1674
src/main/resources/lang/lang_zh.xml
Normal file
1674
src/main/resources/lang/lang_zh.xml
Normal file
File diff suppressed because it is too large
Load Diff
1938
src/main/resources/lang/lang_zh_ref.xml
Normal file
1938
src/main/resources/lang/lang_zh_ref.xml
Normal file
File diff suppressed because it is too large
Load Diff
@ -59,6 +59,8 @@ public class DocuTest extends TestCase {
|
||||
.append(Lang.get("tableOfContent"))
|
||||
.append("\" lang=\"")
|
||||
.append(language)
|
||||
.append("\" fontFamily=\"")
|
||||
.append(language.equals("zh") ? "SansSerif,SimSun" : "SansSerif")
|
||||
.append("\" rev=\"")
|
||||
.append(System.getProperty("buildnumber"))
|
||||
.append("\" revt=\"")
|
||||
|
||||
@ -91,6 +91,13 @@ public class ScreenShots {
|
||||
.set(Keys.SETTINGS_IEEE_SHAPES, true);
|
||||
firstSteps();
|
||||
hierarchicalDesign();
|
||||
|
||||
// Chinese
|
||||
Lang.setActualRuntimeLanguage(new Language("zh"));
|
||||
Settings.getInstance().getAttributes()
|
||||
.set(Keys.SETTINGS_IEEE_SHAPES, true);
|
||||
firstSteps();
|
||||
hierarchicalDesign();
|
||||
}
|
||||
|
||||
private static void mainScreenShot() {
|
||||
@ -316,7 +323,7 @@ public class ScreenShots {
|
||||
.add(new ScreenShot<>(TableDialog.class).useParent())
|
||||
// k-map
|
||||
.press("F10")
|
||||
.press("RIGHT", 5)
|
||||
.press("RIGHT", 4)
|
||||
.press("DOWN", 1)
|
||||
.add(new ScreenShot<>(TableDialog.class).useParent())
|
||||
.press("ENTER")
|
||||
|
||||
@ -6,17 +6,17 @@
|
||||
<xsl:param name="images"><xsl:value-of select="/root/@images"/><xsl:value-of select="/root/@lang"/>/</xsl:param>
|
||||
|
||||
<xsl:template match="root">
|
||||
<fo:root font-family="SansSerif" font-size="11pt" xml:lang="{@lang}">
|
||||
<fo:root font-family="{@fontFamily}" font-size="11pt" xml:lang="{@lang}">
|
||||
<fo:layout-master-set>
|
||||
<fo:simple-page-master master-name="DIN-A4"
|
||||
page-height="29.7cm" page-width="21cm"
|
||||
margin-top="2cm" margin-bottom="1cm"
|
||||
margin-left="2.5cm" margin-right="2.5cm">
|
||||
margin-top="2cm" margin-bottom="1cm"
|
||||
margin-left="2.5cm" margin-right="2.5cm">
|
||||
<fo:region-body
|
||||
margin-top="1.3cm" margin-bottom="1.8cm"
|
||||
margin-left="0cm" margin-right="0cm"/>
|
||||
margin-left="0cm" margin-right="0cm"/>
|
||||
<fo:region-before region-name="header" extent="1.3cm"/>
|
||||
<fo:region-after region-name="footer" extent="1.5cm"/>
|
||||
<fo:region-after region-name="footer" extent="1.5cm"/>
|
||||
<fo:region-start region-name="left" extent="0cm"/>
|
||||
<fo:region-end region-name="right" extent="0cm"/>
|
||||
</fo:simple-page-master>
|
||||
|
||||
@ -112,6 +112,11 @@ the location of this file.
|
||||
for details of FOP configuration for AFP
|
||||
-->
|
||||
|
||||
<!-- specific font mapping chinese -->
|
||||
<font kerning="yes" embed-url="SimSun.ttf" embedding-mode="subset">
|
||||
<font-triplet name="SimSun" style="normal" weight="normal"/>
|
||||
</font>
|
||||
|
||||
<!-- Times Roman -->
|
||||
<font>
|
||||
<afp-font name="Times Roman" type="raster" codepage="T1V10500" encoding="Cp500">
|
||||
|
||||
BIN
src/test/resources/docu/images/zh/scr00.png
Normal file
BIN
src/test/resources/docu/images/zh/scr00.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 42 KiB |
BIN
src/test/resources/docu/images/zh/scr01.png
Normal file
BIN
src/test/resources/docu/images/zh/scr01.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 25 KiB |
BIN
src/test/resources/docu/images/zh/scr02.png
Normal file
BIN
src/test/resources/docu/images/zh/scr02.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 25 KiB |
BIN
src/test/resources/docu/images/zh/scr03.png
Normal file
BIN
src/test/resources/docu/images/zh/scr03.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 44 KiB |
BIN
src/test/resources/docu/images/zh/scr04.png
Normal file
BIN
src/test/resources/docu/images/zh/scr04.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 29 KiB |
BIN
src/test/resources/docu/images/zh/scr05.png
Normal file
BIN
src/test/resources/docu/images/zh/scr05.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 45 KiB |
BIN
src/test/resources/docu/images/zh/scr06.png
Normal file
BIN
src/test/resources/docu/images/zh/scr06.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
BIN
src/test/resources/docu/images/zh/scr07.png
Normal file
BIN
src/test/resources/docu/images/zh/scr07.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
BIN
src/test/resources/docu/images/zh/scr08.png
Normal file
BIN
src/test/resources/docu/images/zh/scr08.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
BIN
src/test/resources/docu/images/zh/scr09.png
Normal file
BIN
src/test/resources/docu/images/zh/scr09.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
BIN
src/test/resources/docu/images/zh/scr10.png
Normal file
BIN
src/test/resources/docu/images/zh/scr10.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 43 KiB |
BIN
src/test/resources/docu/images/zh/scr11.png
Normal file
BIN
src/test/resources/docu/images/zh/scr11.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 34 KiB |
BIN
src/test/resources/docu/images/zh/scr12.png
Normal file
BIN
src/test/resources/docu/images/zh/scr12.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
BIN
src/test/resources/docu/images/zh/scr13.png
Normal file
BIN
src/test/resources/docu/images/zh/scr13.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
BIN
src/test/resources/docu/images/zh/scr14.png
Normal file
BIN
src/test/resources/docu/images/zh/scr14.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 36 KiB |
BIN
src/test/resources/docu/images/zh/scr20.png
Normal file
BIN
src/test/resources/docu/images/zh/scr20.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 46 KiB |
BIN
src/test/resources/docu/images/zh/scr21.png
Normal file
BIN
src/test/resources/docu/images/zh/scr21.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 54 KiB |
BIN
src/test/resources/docu/images/zh/scr22.png
Normal file
BIN
src/test/resources/docu/images/zh/scr22.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 53 KiB |
BIN
src/test/resources/docu/images/zh/scr23.png
Normal file
BIN
src/test/resources/docu/images/zh/scr23.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 56 KiB |
BIN
src/test/resources/docu/images/zh/scr24.png
Normal file
BIN
src/test/resources/docu/images/zh/scr24.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 66 KiB |
BIN
src/test/resources/docu/images/zh/scr25.png
Normal file
BIN
src/test/resources/docu/images/zh/scr25.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 73 KiB |
BIN
src/test/resources/docu/simsun.ttf
Normal file
BIN
src/test/resources/docu/simsun.ttf
Normal file
Binary file not shown.
449
src/test/resources/docu/static_zh.xml
Normal file
449
src/test/resources/docu/static_zh.xml
Normal file
@ -0,0 +1,449 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<root>
|
||||
<chapter heading="Digital">
|
||||
<subchapter heading="简介">
|
||||
<par>
|
||||
Digital 是一个简单的数字电路仿真器。通过导线将各种逻辑门连接起来，可以仿真整个电路的行为。
|
||||
用户可以通过点击按钮或者设置输入值实现交互式仿真。
|
||||
</par>
|
||||
<par>
|
||||
通过这种方式，多数数字电路中的基本电路可以被构建和仿真。在 "examples" 文件夹内，用户可以浏览各种示例，如
|
||||
1个16位的单周期哈佛架构处理器。
|
||||
</par>
|
||||
<par>
|
||||
仿真器有两种操作模式：编辑和仿真模式。
|
||||
在编辑模式，不允许仿真，只允许修改电路。用户可以添加或连接各种组件。
|
||||
可以通过点按工具栏中的 "启动仿真电路" 按钮开启仿真模式。在开始仿真电路之前，将会先检测电路的一致性。
|
||||
如果有某些错误，将会显示对应的消息提示并且相关的组件或导线将会高亮。如果没有任何错误，将会开启仿真模式。这时，
|
||||
你可以和正在运行的仿真进行交互。
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="起步">
|
||||
<par><image src="scr00.png"/></par>
|
||||
<par>
|
||||
作为第一个示例，将会构建一个由异或门组成的电路。在主窗口，"组件" 菜单允许我们选择各种组件。
|
||||
然后它们会被放置于绘图面板。在任何时候，可以通过 ESC 键取消操作。让我们开始选择一个输入组件，该组件在
|
||||
仿真时可以通过鼠标交互进行控制。
|
||||
<par><image src="scr01.png"/></par>
|
||||
<par>
|
||||
选择后，输入组件可以被放置在绘图面板。
|
||||
红色的点表示组件和导线之间的连接点，在之后会被连接。同时红色表示输出，意思为该端口定义了一个信号，该信号可以驱动导线。
|
||||
</par>
|
||||
<par><image src="scr02.png"/></par>
|
||||
<par>
|
||||
使用同样的方式，添加第二个输入组件，最好将其放置在第一个输入组件下面。
|
||||
</par><image src="scr03.png"/></par>
|
||||
<par>
|
||||
添加完输入组件，我们选中异或门。该门表示实际的逻辑功能。
|
||||
</par>
|
||||
<par><image src="scr04.png"/></par>
|
||||
<par>
|
||||
选中后我们可以将其添加到电路。最好将其放置在合适的位置使得后续的连线尽可能简单。蓝色的点表示门的输入端口。
|
||||
</par>
|
||||
<par><image src="scr05.png"/></par>
|
||||
<par>
|
||||
现在，选择一个输出组件，该组件用于显示一个信号状态或者传递信号给一个子电路。
|
||||
</par>
|
||||
<par><image src="scr06.png"/></par>
|
||||
<par>
|
||||
输出组件有一个蓝色的点，意思为输入端口，我们可以通过为其赋值以便之后使用。
|
||||
</par>
|
||||
<par><image src="scr07.png"/></par>
|
||||
<par>
|
||||
当所有组件放置好后，使用鼠标连接蓝色和红色的点。确保仅有一个红色的点被连接到任何蓝色的点。只有允许三态的输出可以
|
||||
打破该规则，允许连接到多个红色的点。当所有导线被绘制后，整个电路即完成。
|
||||
</par>
|
||||
<par><image src="scr08.png"/></par>
|
||||
<par>
|
||||
当仿真启动后，我们可以和电路进行交互。通过点击 “启动仿真电路” 按钮开始仿真。
|
||||
仿真开启后，导线的颜色改变并且输入、输出组件被填充。鲜绿色表示逻辑电平 ‘1’，深绿色表示逻辑电平 ‘0’。
|
||||
在上图中，所有的导线为 ‘0’。
|
||||
</par>
|
||||
<par><image src="scr09.png"/></par>
|
||||
<par>
|
||||
通过鼠标点击，可以切换输入组件的值。由于仿真已经运行，输出组件的值根据当前输入的状态而做出对应改变。电路的行为
|
||||
和期望的异或门一样。
|
||||
</par>
|
||||
<par><image src="scr10.png"/></par>
|
||||
<par>
|
||||
如果需要修改电路，必须先停止仿真。最简单的方式是通过点击工具栏的 “停止” 按钮。
|
||||
通过在组件上右击（MacOS 使用 control+左击）打开组件属性对话框。通过该对话框，我们定义第一个输入组件的标签为 ‘A’。
|
||||
</par>
|
||||
<par><image src="scr11.png"/></par>
|
||||
<par>
|
||||
通过同样的方式，定义剩余组件的输入和输出端口标签。
|
||||
"分析" 菜单包含一个同名的菜单项，该功能对当前电路进行分析。不过，需要先给所有的输入和输出端口添加标签才行。
|
||||
</par>
|
||||
<par><image src="scr12.png"/></par>
|
||||
<par>
|
||||
仿真电路的真值表在一个新窗口中显示，在表的下面，我们可以找到一个和电路对应的布尔表达式。如果电路可能有多个布尔
|
||||
表达式，一个独立的窗口将会打开并显示所有可能的表达式。
|
||||
</par>
|
||||
<par><image src="scr13.png"/></par>
|
||||
<par>
|
||||
真值表对话框有一个 "卡诺图" 菜单项，允许以卡诺图方式显示真值表。
|
||||
</par>
|
||||
<par><image src="scr14.png"/></par>
|
||||
<par>
|
||||
在对话框的顶部，通过下拉列表允许选择期望的表达式。通过这种方式，我们可以评估多个等价的布尔表达式。然而，在该示例中，
|
||||
仅有一个最小表达式。点击卡诺图，可以实现对真值表的修改。
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="导线">
|
||||
<par>
|
||||
所有的组件必须通过导线连接起来。不可以通过将两个组件相邻放置实现连接。
|
||||
</par>
|
||||
<par>
|
||||
另外，仅可以通过导线的端点连接到组件，如果一个组件的管脚放置在一条导线中间，该组件和导线并不会实现连接。
|
||||
因此，导线必须在其所连接的管脚终止。即使使用隧道组件，也必须使用导线连接管脚和隧道组件。
|
||||
</par>
|
||||
<par>
|
||||
如果需要移动组件，包括其连接的导线，则必须先框选该组件，如果不想同时移到其连接的导线，可以通过单击选择组件。
|
||||
</par>
|
||||
<par>
|
||||
通过 CTRL-单击，可以选中且移动或删除一个单独的导线段。如果在画导线时按下 D 键，可以绘制斜线。
|
||||
键 S 可以将一条线段分割为两条。
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="层次设计">
|
||||
<par>
|
||||
随着电路越来越复杂，电路将变得难以理解。为解决该问题，电路中不同的部分可以存放在不同的文件。该机制使得
|
||||
使用子电路变为可能。
|
||||
</par>
|
||||
<par><image src="scr20.png"/></par>
|
||||
<par>
|
||||
作为一个示例，我们考虑4位加法器：首先，我们构建一个简单的半加器，其包含一个异或门和一个与门。
|
||||
位 ‘A’ 和 ‘B’ 相加的结果通过 ‘S’ 和 ‘C’ 输出。该电路存储在文件 "halfAdder.dig"。
|
||||
</par>
|
||||
<par><image src="scr21.png"/></par>
|
||||
<par>
|
||||
使用两个半加器可以构建一个全加器。
|
||||
创建一个空文件并保存为 "fullAdder.dig"，将其放在和半加器相同的路径下。这时，可以通过菜单"组件"<arrow/>"自定义"
|
||||
将半加器添加进电路。
|
||||
半加器的管脚顺序可以在半加器电路中通过菜单 "编辑"<arrow/>"排序输入信号" 或者 "编辑"<arrow/>"排序输出信号"
|
||||
重新排序。全加器实现将位 ‘A’，‘B’，‘Ci’ 相加，结果给到输出 ‘S’ 和 ‘Co’。
|
||||
</par>
|
||||
<par><image src="scr22.png"/></par>
|
||||
<par>
|
||||
为了检验全加器正常工作，我们需要添加一个测试用例。在测试用例中存储满足电路功能的真值表，通过这种方式，可以自动
|
||||
测试电路功能是否正确。
|
||||
</par>
|
||||
<par><image src="scr23.png"/></par>
|
||||
<par>
|
||||
可以通过测试用例编辑器或工具栏中的测试按钮执行测试。
|
||||
绿色高亮的单元格表示电路的输出和测试用例中的真值表相匹配。
|
||||
</par>
|
||||
<par><image src="scr24.png"/></par>
|
||||
<par>
|
||||
现在可以通过全加器进一步构建逐位（行波）进位加法器;。
|
||||
在该示例中，前一个加法器的进位输出作为下一级加法器的进位输入，就像使用纸和笔进行加法一样。
|
||||
为了测试该 4 位加法器的功能，我门添加了一个测试用例。
|
||||
</par>
|
||||
<par><image src="scr25.png"/></par>
|
||||
<par>
|
||||
该测试用例执行 100% 测试，这对于相对简单的电路是可能的。在这里，所有的512种输入组合被应用于电路，同时检测其输出是否
|
||||
正确。
|
||||
第一行列出输入和输出信号，下面的内容应用输入值并检测其对应的输出，像真值表一样。
|
||||
在该示例中，需要512行。然而这样输入即繁琐又容易出错，如果能够自动生成所需要的行，则更容易和可靠。
|
||||
为此，变量 "A" 和 "B" 分别被分别从0到15进行遍历。对应的值被赋值给 ‘A[n]’ 和 ‘B[n]’。然后检测电路输出
|
||||
是否为 "A+B"。然后再次检测当设置进位时，即 "A+B+1" 的对应结果。详细的测试语法可以通过帮助对话框查看。
|
||||
</par>
|
||||
<par>
|
||||
如果一个电路被嵌入另外一个电路，仅仅子电路的名字被保存在父电路而不是子电路本身。
|
||||
因此，在仿真时，必须可以通过文件系统找到对应的子电路。为了避免复杂的导入路径管理，使用以下导入策略。
|
||||
</par>
|
||||
<par>
|
||||
仅仅子电路的文件名而不是完整的文件路径被存储。如果需要打开某个子电路，需要在所有的子文件夹下寻找。
|
||||
该过程仅依赖文件名称而不是完整路径，当在不同路径下有多个同名文件时，将会给出错误信息。
|
||||
</par>
|
||||
<par>
|
||||
一个合理的项目结构看起来应当时这样的：根电路放在独立的文件夹下，所有导入的子电路必须放在相同和子文件夹下。
|
||||
所有的电路必须不能重名，即使位于不同的文件夹内。
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="仿真">
|
||||
<subchapter heading="传输延迟">
|
||||
<par>
|
||||
在仿真时，所有的逻辑门均有一个传输延迟。所有的组件具有相同的传输延迟而与其复杂度无关。
|
||||
因此，与门和乘法器具有相同的传输延迟。特例是二极管，开关和分裂器，这些组件没有任何延迟。
|
||||
</par>
|
||||
<par>
|
||||
如果需要仿真一个组件如乘法器更长的传输延迟，必须在乘法器的输出右侧添加一个延迟组件。
|
||||
</par>
|
||||
<par>
|
||||
如果一个电路被包含进另一个父电路，被包含的电路保持其时序行为。被包含的电路同将其所有组件直接插入父电路行为一致。
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="分析和综合电路">
|
||||
<par>
|
||||
可以通过 "分析" 菜单来分析电路。对于纯组合电路，会生成对应的真值表。可以编辑该真值表，然后从编辑后的真值表生成
|
||||
新的电路。
|
||||
</par>
|
||||
<par>
|
||||
分析和生成时序电路也是可能的。此时，会生成状态转换表而不是简单的真值表。
|
||||
每个触发器在状态转换表的输入和输出侧都会显示。在该表中，右侧为下一个状态，其会在下一个时钟信号产生。
|
||||
下一个状态依赖左侧触发器的当前状态。为了能够分析电路，必须为触发器命名。
|
||||
</par>
|
||||
<par>
|
||||
右侧的下一个状态通过小写的 ‘n+1’ 表示，对应的当前状态通过附加 ‘n’ 表示。如果状态变量为 ‘A’, ‘An’ 表示当前状态，
|
||||
‘An+1’ 表示下一个状态。在一个真值表中，如果信号的名称以此方式命名，则被认为时状态转换表，会生成时序电路而不是组合电路。
|
||||
</par>
|
||||
<par>
|
||||
需要注意的是，需要分析的电路仅可包含纯组合电路和内建的 D、JK 触发器。如果一个触发器由用户自己构建，如使用或非门
|
||||
组成，则该电路不被认为触发器，因此不可以分析这种电路。
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="硬件">
|
||||
<subchapter heading="GAL16v8 和 GAL22v10">
|
||||
<par>
|
||||
在真值表对话框电路生成菜单中，有生成 JEDEC 文件的功能。这是一种描述 PLD 配置图（fuse map）的特殊文件格式。
|
||||
该 JEDEC 文件可以通过特殊的编程器烧写进对应的 PLD 设备。目前，支持 "GAL16v8" 和 "GAL22v10" 或其兼容的设备。
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="ATF150xAS">
|
||||
<par>
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family">
|
||||
"ATF150x"
|
||||
</a>
|
||||
系列芯片是简单的 CPLDs，其最多有128个宏单元。具有 PLCC 封装。这样，如果一个 IC 在实验中被毁坏，那么其可以被
|
||||
简单的替换。另外，通过
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/hardware/atdh1150usb">
|
||||
"ATDH1150USB"
|
||||
</a>
|
||||
廉价和易用的编程器，可以使用 JTAG 接口编程
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family">
|
||||
"ATF150x"
|
||||
</a>
|
||||
芯片。
|
||||
一个合适的评估开发板为
|
||||
<a href="https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATF15XX-DK3-U">
|
||||
("ATF15XX-DK3-U")
|
||||
</a>
|
||||
，编程所需要的软件
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/atmisp">
|
||||
"ATMISP"
|
||||
</a>,
|
||||
通过 ATMEL/Microchip 网站提供。
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="导出 VHDL 或 Verilog">
|
||||
<par>
|
||||
电路可以导出为 VHDL 或 Verilog，导出文件包含电路的完整描述。生成的 VHDL 代码通过了<a href="https://www.xilinx.com/products/design-tools/vivado.html">Xilinx Vivado</a>
|
||||
和开源 VHDL 仿真器 <a href="http://ghdl.free.fr/">ghdl</a> 的测试。Verilog 代码通过了仿真器 <a href="http://iverilog.icarus.com/">Icarus Verilog</a> 的测试。
|
||||
</par>
|
||||
<par>
|
||||
如果电路包含测试用例，测试数据用于生成对应的 HDL 测试平台（test bench），可用于在 HDL 仿真时检测电路功能的正确性。
|
||||
</par>
|
||||
<par>
|
||||
对于一些开发板，会为其生成额外所需的文件。目前，支持 <a href="https://reference.digilentinc.com/reference/programmable-logic/basys-3/start">BASYS3</a>
|
||||
和 Mimas 开发板 <a href="https://numato.com/product/mimas-spartan-6-fpga-development-board">Mimas</a>
|
||||
和 <a href="https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram">Mimas V2</a>。
|
||||
包含管脚分配的约束文件将会被创建。可以在开发板的数据手册中查找其管脚描述，并为输入和输出组件分配管脚编号。
|
||||
</par>
|
||||
<par>
|
||||
对于 BASYS3 板子，如果电路的时钟频率比较低，在生成的 HDL 代码中将包含一个分频器，从而合理的对板载的时钟进行分频。
|
||||
如果电路的时钟频率超过 4.7MHz，则使用 Artix-7 的 MMCM 单元用于生成时钟。
|
||||
</par>
|
||||
<!--par>
|
||||
Also at the Mimas-Boards the Spartan 6 DCM is utilized for the clock generation.
|
||||
</par-->
|
||||
<par>
|
||||
为了创建 HDL 需要的约束文件，必须在设置中配置对应的开发板。在字段 “工具链配置” 中，可以设置对应的 XML 文件。
|
||||
在 "examples/hdl" 目录下，可以找到以 ".config" 为后缀的可用配置文件。
|
||||
如果配置文件正确，会在主菜单右侧显示对应的功能菜单。
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="自定义外观">
|
||||
<par>
|
||||
尽管 Digital 有些内建的选项可以设置子电路的外观，但在某些时候，需要使用更特殊的形状来显示子电路。如当表示处理器
|
||||
中的 ALU 时，本节解释如何为电路定义一个特殊的形状。
|
||||
</par>
|
||||
<par>
|
||||
Digital 没有提供一个用例创建特殊形状的编辑器。
|
||||
为了创建电路形状，需要一些特殊步骤：首先，打开需要创建特殊外观形状的电路，然后为该电路创建一个 SVG 模板，在
|
||||
该模板中，电路表示为一个简单矩形，另外还包含电路中所有的管脚，其中输入使用蓝色圆圈表示，输出使用红色圆圈表示。
|
||||
可以通过查看圆圈的 ID 对象属性了解该圆圈属于哪个管脚。ID 格式为 "pin:[name]" 或 "pin+:[name]"。
|
||||
对于后者，当导入 Digital 时，管脚将被包含一个标签。
|
||||
</par>
|
||||
<par>
|
||||
SVG 文件可以被编辑，如使用最常用的开源编辑器<a href="https://inkscape.org/en/">Inkscape</a>。
|
||||
管脚可以自由移动，但在重新导入 Digital 时，其被替换为最近的栅格坐标位置。
|
||||
</par>
|
||||
<par>
|
||||
当导入Digital后，所有的信息将被提取和保存在电路文件中，SVG 文件不再需要。
|
||||
最后提示：SVG 是一种非常强大和灵活的文件格式。可用于描述非常复杂的图形。
|
||||
Digital 并不能导入所有可能的 SVG 文件。如果一个文件不能被导入，可能会出现异常。
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="通用电路">
|
||||
<par>
|
||||
有这样一种情形，一个子电路用于多种变形。如需要一个不同位宽的计数器，分别用于创建一个 4,5,6位宽的电路，
|
||||
这样，将来维护时会非常困难。因为我们必须维护多个子电路，然而这些子电路除了一个位宽参数，其它都相同。
|
||||
</par>
|
||||
<par>
|
||||
为解决该问题，我们可以创建一个通用参数化的部分电路。
|
||||
为此，电路设置中的 “通用电路” 复选框必须被选中，然后每个组件的属性对话框包含一个额外的字段 “通用参数”。
|
||||
在该字段中，可以输入程序代码用来改变组件的参数。
|
||||
每个参数须有一个名字，可以作为字段"this"的属性被修改。可用参数的名称可以通过组件的帮助对话框查看。
|
||||
如果我们需要改变加法器的位宽，可以通过 "this.Bits=int(1);" 实现，这里的常量 1 始终是 "long"
|
||||
类型，但位宽是 "int"，因此必须使用类型转换。
|
||||
</par>
|
||||
<par>
|
||||
此时，电路仍然没有被参数化。这种情形是必要的，即当电路实际被使用时给出参数。
|
||||
这可以通过 “args” 字段来实现。如果我们想在外部设置位宽，代码可以这样 "this.Bits=int(args.bitWidth);"。
|
||||
参数的名称-这里为 "bitWidth" 是任意的。当实际使用该电路时，需要设置参数 "bitWidth"：。
|
||||
</par>
|
||||
<par>
|
||||
当使用电路时，打开子电路的属性对话框，其也有一个 “通用参数” 字段。这里可以通过输入 "bitWidth:=5;"
|
||||
来实现设置位宽。
|
||||
</par>
|
||||
<par>
|
||||
"examples/generic" 文件夹包含一个格雷码计数器的例子，其位宽可以被配置。
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="使用脚本控制测试">
|
||||
<par>
|
||||
如果学生通过 Digital 来完成测验，能够自动测试学生提交的电路将会非常有帮助。为实现这种测试，可以通过命令行启动 Digital：
|
||||
</par>
|
||||
<par>
|
||||
<code>
|
||||
java -cp Digital.jar de.neemann.digital.testing.CommandLineTester [file to test] [[optional file with
|
||||
test cases]]
|
||||
</code>
|
||||
</par>
|
||||
<par>
|
||||
如果仅指定一个文件，则该文件中的测试用例将被执行。
|
||||
</par>
|
||||
<par>
|
||||
如果指定了第二个文件，则使用第二个文件中的测试用例和第一个文件中的电路进行测试。第二个文件中的电路将被忽略。
|
||||
</par>
|
||||
<par>
|
||||
此时，待测电路和测试用例中的电路输入输出信号名称必须相同。
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="常见问题">
|
||||
<faq>
|
||||
<question>如何移动导线？</question>
|
||||
<answer> 选择其中一个端点或通过 CTRL+单击选择导线，移动鼠标。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如何删除导线？</question>
|
||||
<answer>
|
||||
选择其中一个端点或通过 CTRL+单击选择导线，然后按 "DEL" 键。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如何移动组件，包括其所连接的导线？</question>
|
||||
<answer>框选整个组件
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>当组件管脚放在导线上时没有连接</question>
|
||||
<answer>仅当导线的端点位于管脚时才会连接</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如果管脚的名字比较长，当作为子电路时，管脚名字无法阅读</question>
|
||||
<answer>通过菜单 "编辑<arrow/>设置当前电路" 修改组件的宽度
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>修改子电路管脚的顺序</question>
|
||||
<answer>菜单 "编辑<arrow/>排序输入信号" 或
|
||||
"编辑<arrow/>排序输出信号"</answer>
|
||||
</faq>
|
||||
|
||||
<faq>
|
||||
<question>当开始仿真时，导线颜色变为灰色</question>
|
||||
<answer>
|
||||
鲜绿色表示高电平，深绿色表示低电平，灰色表示高阻。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>我有一个真值表，如何计算最小布尔表达式？</question>
|
||||
<answer>
|
||||
通过菜单 "分析" 选择 "综合"，然后输入真值表。在窗口底部，你会发现匹配的布尔表达式。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>
|
||||
我输入真值表后，显示多个布尔表达式，哪个是正确的？
|
||||
</question>
|
||||
<answer>
|
||||
化简一个布尔表达式可能出现多个结果，它们描述同样的功能
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>我有一个真值表，如何创建对应的电路？</question>
|
||||
<answer>通过菜单 "分析" 选择 "综合"，然后输入真值表。
|
||||
使用菜单 "创建" "电路" 可以创建对应的电路。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如何编辑真值表中信号的名称？</question>
|
||||
<answer>在表头中右击信号名称</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如何根据表达式创建电路？</question>
|
||||
<answer>通过菜单 "分析" "表达式"，输入表达式。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>如何通过表达式创建真值表？</question>
|
||||
<answer>菜单 "分析" "表达式" 输入表达式，创建电路。
|
||||
然后通过菜单 "分析" "分析" 创建真值表。
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>我创建了一个电路，想把它用于很多电路，如何才能不重复的复制到不同的文件夹下？
|
||||
</question>
|
||||
<answer>放在 “lib” 文件夹内
|
||||
</answer>
|
||||
</faq>
|
||||
</chapter>
|
||||
<chapter heading="快捷键" newpage="true">
|
||||
<shortcuts>
|
||||
<shortcut key="Space">开启或停止仿真</shortcut>
|
||||
<shortcut key="F6">打开测量表对话框</shortcut>
|
||||
<shortcut key="F7">运行至中断</shortcut>
|
||||
<shortcut key="F8">执行测试用例</shortcut>
|
||||
<shortcut key="C">时钟步进（仅在仿真模式且只有一个时钟组件时可用）
|
||||
</shortcut>
|
||||
<shortcut key="V">单门步进</shortcut>
|
||||
<shortcut key="B">执行所有单门步骤，直至中断或完成</shortcut>
|
||||
<shortcut key="F9">分析电路</shortcut>
|
||||
<shortcut key="CTRL-A">选择所有</shortcut>
|
||||
<shortcut key="CTRL-X">剪切</shortcut>
|
||||
<shortcut key="CTRL-C">复制</shortcut>
|
||||
<shortcut key="CTRL-V">从剪贴板插入</shortcut>
|
||||
<shortcut key="CTRL-D">复制当前选中而不更改剪贴板</shortcut>
|
||||
<shortcut key="R">旋转组件</shortcut>
|
||||
<shortcut key="L">插入最近一次插入的组件</shortcut>
|
||||
<shortcut key="T">插入隧道组件</shortcut>
|
||||
<shortcut key="CTRL-N">新建电路</shortcut>
|
||||
<shortcut key="CTRL-O">打开电路</shortcut>
|
||||
<shortcut key="CTRL-S">保存电路</shortcut>
|
||||
<shortcut key="CTRL-Z">撤销上次修改</shortcut>
|
||||
<shortcut key="CTRL-Y">重做上次撤销操作</shortcut>
|
||||
<shortcut key="P">对二极管或浮动栅场效应管编程</shortcut>
|
||||
<shortcut key="D">画导线时使用对角线模式</shortcut>
|
||||
<shortcut key="F">画线时翻转方向</shortcut>
|
||||
<shortcut key="S">分割一条导线为两条</shortcut>
|
||||
<shortcut key="ESC">放弃当前操作</shortcut>
|
||||
<shortcut key="Del">删除</shortcut>
|
||||
<shortcut key="Backspace">删除</shortcut>
|
||||
<shortcut key="+">
|
||||
加1
|
||||
</shortcut>
|
||||
<shortcut key="-">减1
|
||||
</shortcut>
|
||||
<shortcut key="CTRL +">放大</shortcut>
|
||||
<shortcut key="CTRL -">缩小</shortcut>
|
||||
<shortcut key="F1">适合窗口</shortcut>
|
||||
<shortcut key="F5">显示或隐藏组件树</shortcut>
|
||||
</shortcuts>
|
||||
</chapter>
|
||||
</root>
|
||||
741
src/test/resources/docu/static_zh_ref.xml
Normal file
741
src/test/resources/docu/static_zh_ref.xml
Normal file
@ -0,0 +1,741 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<root>
|
||||
<chapter heading="Digital">
|
||||
<subchapter heading="Introduction">
|
||||
<par>
|
||||
Digital is a simple simulator used to simulate digital circuits. The logic gates are connected
|
||||
to each other by wires and the behavior of the overall circuit can be simulated.
|
||||
The user can interact with the simulation by either pressing buttons or setting
|
||||
values to the inputs of the circuit.
|
||||
</par>
|
||||
<par>
|
||||
In this way, most of the basic circuits used in digital electronics can be built and simulated.
|
||||
In the folder <e>examples</e>, users can browse for examples that includes a functional
|
||||
16-bit single-cycle Harvard processor.
|
||||
</par>
|
||||
<par>
|
||||
The simulator has two modes of operation: Editing and Simulation mode.
|
||||
In the editing mode, modifications to the circuit can be performed. Users can add or connect components.
|
||||
In this mode, simulation is disabled.
|
||||
The simulation mode is activated by pressing the <e>Start</e> button in the tool bar.
|
||||
While starting the simulation the circuit is checked for consistency.
|
||||
If there are errors in the circuit an appropriate message is shown and
|
||||
the affected components or wires are highlighted. If the circuit is error free, the simulation is
|
||||
enabled. Now you can interact with the running simulation.
|
||||
In the simulation mode it is not possible to modify the circuit. To do so you have to activate the
|
||||
editing mode again by stopping the simulation.
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="First Steps">
|
||||
<par>
|
||||
<image src="scr00.png"/>
|
||||
</par>
|
||||
<par>
|
||||
As a first example, a circuit is to be constructed with an Exclusive-Or gate.
|
||||
From the main window, the <e>Components</e> menu allows you to select the various components.
|
||||
Then they are placed on the drawing panel. This process can be canceled by pressing the ESC key at any
|
||||
time. Start by selecting an input component.
|
||||
This can later be controlled interactively by using the mouse.
|
||||
<par>
|
||||
<image src="scr01.png"/>
|
||||
</par>
|
||||
<par>
|
||||
After selection, the first input can be placed on the drawing panel.
|
||||
The red dot on the input component symbol is a connection point between the component and a wire,
|
||||
which will be
|
||||
connected later on.
|
||||
The red color indicates an output. This means that the port defines a signal value or can drive a
|
||||
wire.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr02.png"/>
|
||||
</par>
|
||||
<par>
|
||||
In the same way, a second input is added. It is best to place it directly below the first input.
|
||||
</par>
|
||||
<image src="scr03.png"/>
|
||||
</par>
|
||||
<par>
|
||||
After adding the inputs, the Exclusive-Or gate is selected. This gate represents the actual logical
|
||||
function.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr04.png"/>
|
||||
</par>
|
||||
<par>
|
||||
This gate can now also be added to the circuit. It is best to place it in a way that the subsequent
|
||||
wiring is made as simple as possible. The blue dots indicate the input terminals of the gate.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr05.png"/>
|
||||
</par>
|
||||
<par>
|
||||
Now, select an output which could be used to display a signal state or to later pass signals to
|
||||
an embedding circuit.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr06.png"/>
|
||||
</par>
|
||||
<par>
|
||||
This is placed in a way that it can be wired easily.
|
||||
The output has a blue dot, which indicates an input terminal.
|
||||
Here you can feed in the value which is then exported.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr07.png"/>
|
||||
</par>
|
||||
<par>
|
||||
After all components are selected and in place, use the mouse to wire a connection between the blue and
|
||||
red dots. Make sure that exactly one red dot is connected to any number of blue dots.
|
||||
Only the usage of three-state outputs makes it possible to deviate from this rule and to interconnect
|
||||
several red dots.
|
||||
If all wires have been drawn, the circuit is complete.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr08.png"/>
|
||||
</par>
|
||||
<par>
|
||||
Interaction with the circuit is possible when simulation is started.
|
||||
This is done by clicking on the play button located in the toolbar.
|
||||
After starting the simulation, the color of the wires changes and the
|
||||
inputs and outputs are now filled. Bright green indicates a logical '1' and dark green a logical '0'.
|
||||
In the figure above, all wires have a '0' value.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr09.png"/>
|
||||
</par>
|
||||
<par>
|
||||
By clicking with the mouse, the inputs can be switched. Since the simulation is now active, the
|
||||
output changes according to the current input states. The circuit behaves like an
|
||||
Exclusive-Or gate as expected .
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr10.png"/>
|
||||
</par>
|
||||
<par>
|
||||
To further process the circuit, the simulation must first be stopped. The easiest way to do this is
|
||||
with the Stop button in the tool bar. Clicking on a component with the right mouse button
|
||||
(control-click on MacOS) opens a dialog which shows the component's properties. The label 'A' can
|
||||
be defined for the first input via this dialog.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr11.png"/>
|
||||
</par>
|
||||
<par>
|
||||
In this way, the labels for the remaining inputs and outputs can be defined. The menu item
|
||||
<e>Analysis</e>
|
||||
also contains a menu item <e>Analysis</e>. This function performs an analysis of
|
||||
the current circuit. However, this is only possible if all inputs and outputs are labeled properly.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr12.png"/>
|
||||
</par>
|
||||
<par>
|
||||
The truth table of the simulated circuit appears in a new window. Below the table you can find the
|
||||
algebraic expression associated with the circuit. If there are several possible algebraic
|
||||
expressions, a separate window will open, showing all possible expressions.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr13.png"/>
|
||||
</par>
|
||||
<par>
|
||||
The table dialog has the menu entry <e>K-Map</e> in its main menu. This allows to display the truth
|
||||
table in the form of a K-map.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr14.png"/>
|
||||
</par>
|
||||
<par>
|
||||
At the top of this dialog there is a drop-down list which allows the selection of the desired
|
||||
expression in the K-map. In this way you can, for example, illustrate how several equivalent
|
||||
algebraic expressions can result. However, in this example, there is only one minimal expression.
|
||||
The truth table can also be modified by clicking the K-map.
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="Wires">
|
||||
<par>
|
||||
All components must be connected via wires. It is not possible to connect two components
|
||||
by placing them directly next to each other.
|
||||
</par>
|
||||
<par>
|
||||
In addition, there are only connections between an endpoint of a wire and a component.
|
||||
If a pin of a component is placed in the middle of a wire, no connection is made between the component
|
||||
and the wire.
|
||||
Therefore, a wire must actually terminate at each pin which is to be connected.
|
||||
Even if the tunnel component is used, there must be a wire between the pin and the tunnel element.
|
||||
</par>
|
||||
<par>
|
||||
The component needs to be selected using the rectangular selection tool in order to be moved,
|
||||
including the connected wires. For moving a component without the connected wires,
|
||||
select the component using a mouse click.
|
||||
</par>
|
||||
<par>
|
||||
With CTRL-Click a single wire section can be selected to move or delete it.
|
||||
If the D key is pressed while drawing a wire, a diagonal wire can be drawn.
|
||||
The key S allows the splitting of a line segment into two segments.
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="Hierarchical Design">
|
||||
<par>
|
||||
If a complex circuit is built up, this can quickly become very confusing. To keep track here,
|
||||
the different parts of a circuit can be stored in different files. This mechanism also makes it
|
||||
possible to use a subcircuit, which has been created once, several times in a further circuit.
|
||||
This approach also offers the advantage that the files can be stored independently of each other in a
|
||||
version control system and changes can be tracked.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr20.png"/>
|
||||
</par>
|
||||
<par>
|
||||
As an example, consider a 4-bit adder: First, we built a simple half-adder. This consists of an
|
||||
XOR gate and an AND gate. The sum of the two bits 'A' and 'B' is given to the outputs 'S' and 'C'.
|
||||
This circuit is stored in the file <e>halfAdder.dig</e>.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr21.png"/>
|
||||
</par>
|
||||
<par>
|
||||
From two half adders a full adder can now be built. To do this, create a new empty file and save the
|
||||
empty file as <e>fullAdder.dig</e> in the same folder as the half adder. Then the
|
||||
half adder can be added to the new circuit via the
|
||||
<e>Components</e>
|
||||
<arrow/>
|
||||
<e>Custom</e>
|
||||
menu.
|
||||
The order of the pins at the package of the half-adder can be rearranged in the half adder in the
|
||||
menu
|
||||
<e>Edit</e>
|
||||
<arrow/>
|
||||
<e>Order inputs</e>
|
||||
or
|
||||
<e>Edit</e>
|
||||
<arrow/>
|
||||
<e>Order outputs</e>.
|
||||
The full adder adds the three bits 'A', 'B' and 'Ci' and gives the sum to the outputs 'S' and 'Co'.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr22.png"/>
|
||||
</par>
|
||||
<par>
|
||||
In order to check the correct function of the full adder, a test case should be added. In the test case,
|
||||
the truth table is stored, which should fulfill the circuit. In this way it can be automatically
|
||||
checked whether this is the case.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr23.png"/>
|
||||
</par>
|
||||
<par>
|
||||
The tests can be executed via the test case editor or the test button in the toolbar.
|
||||
The table cells highlighted in green indicate that the output of the circuit matches
|
||||
the truth table given in the test case.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr24.png"/>
|
||||
</par>
|
||||
<par>
|
||||
Now the full adders can be put together to form a so-called ripple-carry adder.
|
||||
In this case, the carry output of an addition is forwarded as a carry input to the addition of the
|
||||
next higher-order bit, just as is usual in pencil-and-paper addition.
|
||||
This 4-bit adder should be tested for correct function. For this purpose a test case was inserted.
|
||||
</par>
|
||||
<par>
|
||||
<image src="scr25.png"/>
|
||||
</par>
|
||||
<par>
|
||||
This test case performs a 100% test, which is possible only with relatively simple circuits: all
|
||||
possible 512 input combinations are applied to the circuit, and it is checked whether the output
|
||||
of the circuit is correct.
|
||||
The first line lists the input and output signals. Below this, the input values to be applied and
|
||||
the output values to be checked are specified in a row, as in a truth table.
|
||||
In this example, however, 512 lines are required. Entering this would be a tedious and error-prone task.
|
||||
It is easier and more reliable to automatically generate the required lines.
|
||||
For this purpose, the variables <e>A</e> and <e>B</e> are each traversed
|
||||
from 0 to 15. The respective values of <e>A</e> and <e>B</e> are then assigned to inputs 'A[n]' and
|
||||
'B[n]'.
|
||||
Then it is checked whether the circuit outputs the value <e>A+B</e>. Then it is checked again with
|
||||
the carry bit set, in which case <e>A+B+1</e> must result.
|
||||
The details of the test syntax are provided by the help dialog.
|
||||
</par>
|
||||
<par>
|
||||
If a circuit is embedded in an other circuit, only the file name of the subcircuit is stored in a
|
||||
circuit, not the embedded circuit itself.
|
||||
The corresponding files of
|
||||
the embedded subcircuits must therefore be found in the file system at runtime of the simulation.
|
||||
In order to support the various work methods of the users as best as possible and still to avoid a
|
||||
complex administration of import paths, etc., a somewhat unusual import strategy is implemented.
|
||||
</par>
|
||||
<par>
|
||||
Only the file names of the embedded circuits are stored in a circuits file, not the full path.
|
||||
If a file needs to be opened, all subfolders are searched for a file of the corresponding name.
|
||||
If a suitable file is found, it is imported. This process only depends on the file name of the file to
|
||||
be read, not on its path. Correspondingly, an error message is generated if there are several files of
|
||||
the same name in different subfolders, since ambiguities then arise.
|
||||
</par>
|
||||
<par>
|
||||
A suitable project structure therefore looks as follows: The root circuit is located in a separate
|
||||
folder.
|
||||
All imported circuits must be in the same folder or subfolders. All circuits must have different names,
|
||||
so it must not happen that there are circuits of the same name in different folders.
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="Simulation">
|
||||
<subchapter heading="Propagation Delay">
|
||||
<par>
|
||||
During the simulation every logic gate has a propagation delay. Every component found in the library
|
||||
has the same propagation delay regardless of its complexity.
|
||||
The AND gate thus has the same propagation delay as the multiplier.
|
||||
The only exceptions are diodes, switches and splitters which are used to create data buses.
|
||||
These components have no propagation delay at all.
|
||||
</par>
|
||||
<par>
|
||||
If it's necessary to simulate a gate - e.g. the multiplier - with a longer propagation delay, a delay
|
||||
gate must be inserted in the circuit right behind the output of the multiplier.
|
||||
</par>
|
||||
<par>
|
||||
If a circuit is included in another parent circuit, the included circuit keeps its timing behaviour.
|
||||
So if you include a complex circuit which has a large propagation delay because the input signals
|
||||
has to pass three gates until it reaches the output, this behaviour is conserved while including this
|
||||
circuit.
|
||||
There are no additional delays introduced as a result of including a circuit. If not all outputs of a
|
||||
circuit have
|
||||
the same propagation delay, then this is also the case if it is included in a parent circuit.
|
||||
In general, including a circuit into an other circuit does not modify its timing behaviour at all. An
|
||||
included circuit behaves exactly the same way as if all components had been inserted at the same circuit
|
||||
level.
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="Circuit Analysis and Synthesis">
|
||||
<par>
|
||||
A circuit can be analyzed via the menu entry <e>Analysis</e>. A truth table is generated for purely
|
||||
combinatorial circuits. This truth table can be edited as desired.
|
||||
A new circuit can be generated from this truth table after editing.
|
||||
</par>
|
||||
<par>
|
||||
In addition to purely combinatorial circuits, it is also possible to analyze or generate sequential
|
||||
circuits.
|
||||
Instead of a simple truth table a so-called state transition table is created.
|
||||
Each flip-flop thereby appears on the input side and the output side of the state transition table.
|
||||
In this table, on the right-hand side, you can find the next state, which will
|
||||
occur after the next clock signal. This next state depends on the current state of the flip-flops as found
|
||||
at the left-hand side of the table.
|
||||
For an analysis to be possible, the flip-flops must be named.
|
||||
</par>
|
||||
<par>
|
||||
The following naming convention applies: The following next state of a bit on the right side of the table
|
||||
is indicated by a lowercase 'n+1'. The corresponding current state is indicated by an appended 'n'.
|
||||
If there is a state variable 'A', 'An' indicates the current state and 'An+1' indicates the next state.
|
||||
If, in the truth table on the left and right side, signals are present, which correspond to this pattern
|
||||
it is assumed that the table is a state transition table, and a sequential circuit is generated instead of
|
||||
a combinatorial circuit.
|
||||
</par>
|
||||
<par>
|
||||
It should be noted that the circuit to be analyzed may contain only purely combinatorial elements in
|
||||
addition to the built-in D and JK flip-flops. If a flip-flop is e.g. made from Nor gates, this
|
||||
circuit is not recognized as a flip-flop and therefore it is not possible to analyse such a circuit.
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="Hardware">
|
||||
<subchapter heading="GAL16v8 and GAL22v10">
|
||||
<par>
|
||||
In the circuit generation menu in the truth table there are also functions to generate so-called
|
||||
JEDEC files. This is a special file format that describes the fuse map of a PLD.
|
||||
This JEDEC file can be written into a corresponding PLD using a special programmer.
|
||||
At the moment, circuits of the type <e>GAL16v8</e> and <e>GAL22v10</e> or fuse map compatible
|
||||
devices are supported.
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="ATF150xAS">
|
||||
<par>
|
||||
The chips in the
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family">
|
||||
<e>ATF150x</e>
|
||||
</a>
|
||||
family are simple CPLDs with up to 128 macrocells. They are available in a
|
||||
PLCC package, which makes them suitable for laboratory exercises: If an IC is destroyed during
|
||||
exercises,
|
||||
it can simply be replaced. In addition, with the
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/hardware/atdh1150usb">
|
||||
<e>ATDH1150USB</e>
|
||||
</a>
|
||||
an easy to use, low-cost programmer is available. This programmer is able to program the
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family">
|
||||
<e>ATF150x</e>
|
||||
</a>
|
||||
chips in system using a JTAG interface.
|
||||
A suitable evaluation board
|
||||
<a href="https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATF15XX-DK3-U">
|
||||
(<e>ATF15XX-DK3-U</e>)
|
||||
</a>
|
||||
is also available.
|
||||
The software
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/atmisp">
|
||||
<e>ATMISP</e>
|
||||
</a>
|
||||
,
|
||||
which is available on the ATMEL/Microchip website, is required for programming the chips.
|
||||
</par>
|
||||
<par>
|
||||
Unfortunately, the fuse map details are not publicly available so that no suitable fitter for this chip
|
||||
can be integrated in Digital, as is possible with the <e>GAL16v8</e> and <e>GAL22v10</e> chips.
|
||||
</par>
|
||||
<par>
|
||||
Therefore, the fitters <e>fit150[x].exe</e> provided by ATMEL must be used. These programs create a
|
||||
<e>JEDEC</e>
|
||||
file from a suitable <e>TT2</e> file which can then be programmed on the chip. Digital
|
||||
starts the fitter automatically every time a <e>TT2</e> file is created. For this purpose, the path to
|
||||
the
|
||||
<e>fit150[n].exe</e>
|
||||
fitters must be specified in the settings.
|
||||
The created <e>JEDEC</e> file can then be opened and programmed directly with
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/atmisp">
|
||||
<e>ATMISP</e>
|
||||
</a>
|
||||
.
|
||||
</par>
|
||||
<par>
|
||||
For legal reasons the fitter <e>fit1502.exe</e> can not be distributed with Digital. However, it can be
|
||||
found in the folder <e>WinCupl\Fitters</e> after installing
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/wincupl">
|
||||
<e>WinCupl</e>
|
||||
</a>
|
||||
.
|
||||
<a href="https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/wincupl">
|
||||
<e>WinCupl</e>
|
||||
</a>
|
||||
is available on the ATMEL/Microchip website.
|
||||
On Linux systems, the fitters can also be executed by Digital if <e>wine</e> is installed.
|
||||
</par>
|
||||
</subchapter>
|
||||
<subchapter heading="Export to VHDL or Verilog">
|
||||
<par>
|
||||
A circuit can be exported to VHDL or Verilog. A file is generated which contains the complete
|
||||
description
|
||||
of the circuit. The generated VHDL code was tested with
|
||||
<a href="https://www.xilinx.com/products/design-tools/vivado.html">Xilinx Vivado</a>
|
||||
and the open source VHDL simulator <a href="http://ghdl.free.fr/">ghdl</a>.
|
||||
The Verilog code is tested with the Verilog simulator <a href="http://iverilog.icarus.com/">Icarus
|
||||
Verilog</a>.
|
||||
</par>
|
||||
<par>
|
||||
If a circuit contains test cases, the test data is used to generate a HDL test bench. This can be used
|
||||
to check the correct function of the circuit in a HDL simulation.
|
||||
</par>
|
||||
<par>
|
||||
Additional files which are needed by special boards can be created. At present only the
|
||||
<a href="https://reference.digilentinc.com/reference/programmable-logic/basys-3/start">BASYS3</a>
|
||||
board and the Mimas boards
|
||||
<a href="https://numato.com/product/mimas-spartan-6-fpga-development-board">Mimas</a>
|
||||
and
|
||||
<a href="https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram">Mimas V2
|
||||
</a>
|
||||
are supported.
|
||||
A constraints file is created, which contains the assignment of the pins. The description of the pins
|
||||
can
|
||||
be found in the boards data sheet, and must be entered as a pin number for the inputs and outputs.
|
||||
</par>
|
||||
<par>
|
||||
At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL
|
||||
code to divide the board clock accordingly.
|
||||
If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the
|
||||
Artix-7 is used for clock generation.
|
||||
This ensures that the FPGA resources provided for the clock distribution are used.
|
||||
This allows the included example processor to run at 20MHz, and if you can do without the
|
||||
multiplier, 30HMz is also possible.
|
||||
</par>
|
||||
<!--par>
|
||||
Also at the Mimas-Boards the Spartan 6 DCM is utilized for the clock generation.
|
||||
</par-->
|
||||
<par>
|
||||
If a circuit is to run on a BASYS3 board, a new project can be created in Vivado.
|
||||
The generated VHDL file and the constraints file must be added to the project.
|
||||
Once the project has been created, the bitstream can be generated and the Hardware-Manager can be used
|
||||
to program a BASYS3 board.
|
||||
</par>
|
||||
<par>
|
||||
In order to create the required constraints file in addition to the HDL file, the corresponding board
|
||||
must be configured in the settings. In the field "Toolchain Configuration" the corresponding XML file
|
||||
can be selected.
|
||||
The available configurations can be found in the folder <e>examples/hdl</e> and have the file
|
||||
extension <e>.config</e>.
|
||||
If the configuration was successfully integrated, a further menu appears, which makes the board
|
||||
specific functions accessible.
|
||||
</par>
|
||||
</subchapter>
|
||||
</chapter>
|
||||
<chapter heading="Custom Shapes">
|
||||
<par>
|
||||
Although Digital has some options that determine the appearance of a circuit when it is embedded in
|
||||
another, in some cases it may be useful to use a very special shape for a subcircuit. An example is
|
||||
the representation of the ALU in the processor included in the examples. This chapter explains how to
|
||||
define such a special shape for a circuit.
|
||||
</par>
|
||||
<par>
|
||||
Digital does not provide an editor for creating a special shape. Instead, a small detour is required
|
||||
for creating circuit shapes: First, the circuit is opened, which is to be represented by a special shape.
|
||||
Then an SVG template is created for this circuit. In this template, the circuit is represented by a
|
||||
simple rectangle. It also contains all the pins of the circuit, represented by blue (inputs) and
|
||||
red (outputs) circuits. To see which circle belongs to which pin, you can look at the ID of the
|
||||
circle in the object properties. This ID has the form <e>pin:[name]</e> or <e>pin+:[name]</e>.
|
||||
In the latter variant, the pin is provided with a label if reimported to digital.
|
||||
If you do not want such a label, the <e>+</e> can be removed.
|
||||
</par>
|
||||
<par>
|
||||
This SVG file can now be edited. The most suitable is the open source program
|
||||
<a href="https://inkscape.org/en/">Inkscape</a>
|
||||
which is available for free.
|
||||
The pins can be moved freely, but are moved to the next grid point during the reimport.
|
||||
</par>
|
||||
<par>
|
||||
If existing SVG files are to be used, it is easiest to open the created template and paste the
|
||||
existing graphic into the template via Copy&Paste.
|
||||
</par>
|
||||
<par>
|
||||
If the file was saved, it can be imported with Digital. The file is read in and all necessary
|
||||
information is extracted and stored in the circuit. For further use of the circuit, the SVG
|
||||
file is no longer required.
|
||||
</par>
|
||||
<par>
|
||||
A final remark: SVG is a very powerful and flexible file format.
|
||||
It can be used to describe extremely complex graphics. The Digital importer is not able to import all
|
||||
possible SVG files without errors. If a file can not be imported, or does not appear as expected,
|
||||
some experimentation may be required before the desired result is achieved.
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="Generic Circuits">
|
||||
<par>
|
||||
It happens that a subcircuit has been created, and this is to be used in different variants.
|
||||
For example, you can imagine a special counter that is needed for different bit widths.
|
||||
If one would create a partial circuit for 4, 5 and 6 bits each, the maintenance of the circuit
|
||||
would be difficult in the future, since one must always work on several subcircuits, which are
|
||||
identical except for one parameter, the bit width.
|
||||
</par>
|
||||
<par>
|
||||
To prevent this, a generic partial circuit can be created which can be parameterized.
|
||||
For this purpose, the checkbox "Circuit is generic" must be set in the circuit setting of the circuit.
|
||||
Then the parameter dialog of each component of the circuit contains the additional field "generic
|
||||
parameterization". In this field program code can be entered, which can change the parameters of the
|
||||
component. Each parameter has a name and can be modified as an attribute of the field <e>this</e>.
|
||||
The names of the parameters can be found in the help dialog of the component.
|
||||
If you want to change the bit width of an adder, the line <e>this.Bits=int(1);</e> can be used.
|
||||
Constants - here the one - are always of type <e>long</e>, but the bit width is an <e>int</e>.
|
||||
Therefore the type conversion to an <e>int</e> is necessary.
|
||||
</par>
|
||||
<par>
|
||||
In this way, however, it is not yet possible to create a circuit that can be parameterized.
|
||||
It is still necessary to access parameters that are set when the circuit is used.
|
||||
This is done via the field "args". If you want to set the bit width from outside, you can write:
|
||||
<e>this.Bits=int(args.bitWidth);</e>. The name of the argument - here <e>bitWidth</e> is arbitrary.
|
||||
If this partial circuit is used, this argument must be set.
|
||||
</par>
|
||||
<par>
|
||||
If the circuit is used and the parameter dialog of the embedded circuit is opened, it also has a
|
||||
field "generic parameterization". Here the bit width to be used can be set with the instruction
|
||||
<e>bitWidth:=5;</e>.
|
||||
</par>
|
||||
<par>
|
||||
In this way, no wires or components can be removed or added. Nevertheless, many circuits can be
|
||||
realized with a trick. This is achieved by replacing one circuit with another, depending on the
|
||||
arguments. For this purpose the function <e>setCircuit([Name])</e> is available.
|
||||
If it is called in the definition part of a subcircuit, the circuit to be inserted can be replaced
|
||||
by another circuit. This allows the recursive definition of a circuit. As in other programming
|
||||
languages, a suitable termination condition must be ensured.
|
||||
</par>
|
||||
<par>
|
||||
The <e>examples/generic</e> folder contains an example of a Gray code counter whose bit width can
|
||||
be configured. Here a Gray code counter is constructed by recursively adding further bits to an
|
||||
initial circuit until the required number of bits of the counter is reached.
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="Script-controlled testing">
|
||||
<par>
|
||||
If students are to complete exercises with Digital, it can be helpful if the circuits submitted by the
|
||||
students can be checked in an automatic process. To perform this check, Digital can be started
|
||||
from the command line. The call is done as follows:
|
||||
</par>
|
||||
<par>
|
||||
<code>
|
||||
java -cp Digital.jar de.neemann.digital.testing.CommandLineTester [file to test] [[optional file with
|
||||
test cases]]
|
||||
</code>
|
||||
</par>
|
||||
<par>
|
||||
If only the file to be tested is specified, the test cases in that file are executed. In this way, the
|
||||
test cases created by the students themselves can be executed.
|
||||
</par>
|
||||
<par>
|
||||
If a second file name is specified, the test cases are taken from the second file and the first circuit
|
||||
is checked with these test cases. The second file will therefore usually contain the sample solution
|
||||
whose test cases are complete and correct. The circuit contained in the second file is ignored.
|
||||
Only the test cases are taken from it.
|
||||
</par>
|
||||
<par>
|
||||
In order to test a submitted circuit against a sample solution, the signal names of the inputs and
|
||||
outputs in both circuits must match.
|
||||
</par>
|
||||
</chapter>
|
||||
<chapter heading="Frequently asked Questions">
|
||||
<faq>
|
||||
<question>How to move a wire?</question>
|
||||
<answer>Select one of the end points with the rectangular selection. Then move this point using the mouse.
|
||||
You can also select a wire with CTRL + mouse button.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>How to delete a wire?</question>
|
||||
<answer>Select one of the end points and press <e>DEL</e> or click on the trashcan.
|
||||
You can also select a wire with CTRL + mouse button.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>How to move a component including all the connected wires?</question>
|
||||
<answer>Select the component with the rectangular selection. The selection must include the entire
|
||||
component.
|
||||
Then move the component including the wires using the mouse.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>There is a component not connected to a wire, even though the pins are on the wire.</question>
|
||||
<answer>A pin is only connected to a wire if the wire has an endpoint at the pin.</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>If the names of the pins in a circuit are long, the names are no longer readable when
|
||||
the circuit is embedded. What can I do?
|
||||
</question>
|
||||
<answer>The width of the block can be increased using the menu item
|
||||
<e>Edit<arrow/>Edit circuit attributes
|
||||
</e>
|
||||
.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>The pins in an embedded circuit have an non-optimal order. How can this be changed?</question>
|
||||
<answer>The sequence can be changed using the menu entry
|
||||
<e>Edit<arrow/>Order inputs
|
||||
</e>
|
||||
or
|
||||
<e>Edit<arrow/>Order outputs
|
||||
</e>
|
||||
.
|
||||
</answer>
|
||||
</faq>
|
||||
|
||||
<faq>
|
||||
<question>When the simulation is started, a wire becomes gray. What does that mean?</question>
|
||||
<answer>The colors light green and dark green are used to represent high and low state.
|
||||
Gray means the wire is in high Z state.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have a truth table. How to calculate the minimized boolean equations?</question>
|
||||
<answer>In the menu <e>Analysis</e> select the entry <e>Synthesise</e>. Then enter the truth table.
|
||||
At the bottom of the window you can find the matching boolean equation. If you enter more than one
|
||||
dependent variable, a new window opens in which all boolean equations are shown.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have entered a truth table, but there is more than one boolean equation shown.
|
||||
Which of them is the correct one?
|
||||
</question>
|
||||
<answer>Minimizing a boolean equation can result in many equations, describing the same function.
|
||||
Digital shows all of them and they all create the same truth table.
|
||||
There may be differences depending on the "don't cares" in the truth table.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have a truth table. How to create a circuit representing the truth table?</question>
|
||||
<answer>In the menu <e>Analysis</e> select the entry <e>Synthesise</e>. Then enter the truth table.
|
||||
You can edit the table using the <e>New</e> or <e>Add Columns</e> menus.
|
||||
In the menu <e>Create</e> you can create a circuit using the <e>Circuit</e> item.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>How to edit a signal's name in the truth table?</question>
|
||||
<answer>Right click on the name in the table header to edit the name.</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have a boolean equation. How to create a circuit?</question>
|
||||
<answer>In the menu <e>Analysis</e> select the entry <e>Expression</e>. Then enter the expression.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>How to create a truth table from a boolean equation?</question>
|
||||
<answer>In the menu <e>Analysis</e> select the entry <e>Expression</e>. Then enter the expression.
|
||||
Then create a circuit and in the menu <e>Analysis</e> use the entry <e>Analysis</e> to create the truth
|
||||
table.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>How to create a JEDEC file from a given circuit?</question>
|
||||
<answer>In the menu <e>Analysis</e> select the entry <e>Analysis</e>. Then in the menu <e>Create</e> in the
|
||||
new
|
||||
window choose the correct device in the sub menu <e>Device</e>.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>When creating a JEDEC file: How to assign a pin number to a certain signal?</question>
|
||||
<answer>At the corresponding inputs and outputs you can enter a pin number in the settings dialog of the
|
||||
pin.
|
||||
</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have created a JEDEC file. How to program it to a <e>GAL16v8</e> or <e>GAL22v10</e>?
|
||||
</question>
|
||||
<answer>To program such a chip a special programmer hardware is necessary.</answer>
|
||||
</faq>
|
||||
<faq>
|
||||
<question>I have created a circuit that I want to use in many other circuits.
|
||||
How can I do this without copying the file over and over again into the appropriate folders?
|
||||
</question>
|
||||
<answer>The circuit can be saved in the "lib" folder. Then it is available in all other circuits.
|
||||
</answer>
|
||||
</faq>
|
||||
</chapter>
|
||||
<chapter heading="Keyboard Shortcuts" newpage="true">
|
||||
<shortcuts>
|
||||
<shortcut key="Space">Starts or stops the simulation.</shortcut>
|
||||
<shortcut key="F6">Opens the measurement table dialog.</shortcut>
|
||||
<shortcut key="F7">Run to Break</shortcut>
|
||||
<shortcut key="F8">Execute test cases</shortcut>
|
||||
<shortcut key="C">A single clock step (Works only in a running simulation and only if there is a single
|
||||
clock component).
|
||||
</shortcut>
|
||||
<shortcut key="V">Execute a single gate step.</shortcut>
|
||||
<shortcut key="B">Execute all single gate steps until the circuit has stabilized or,
|
||||
if a break component is present, until the break.
|
||||
</shortcut>
|
||||
<shortcut key="F9">Analysis of the circuit</shortcut>
|
||||
<shortcut key="CTRL-A">Select all.</shortcut>
|
||||
<shortcut key="CTRL-X">Cuts the selected components to the clipboard.</shortcut>
|
||||
<shortcut key="CTRL-C">Copys the selected components to the clipboard.</shortcut>
|
||||
<shortcut key="CTRL-V">Inserts the components from the clipboard.</shortcut>
|
||||
<shortcut key="CTRL-D">Duplicate the current selection without modifying the clipboard.</shortcut>
|
||||
<shortcut key="R">While inserting this rotates the components.</shortcut>
|
||||
<shortcut key="L">Inserts the last inserted component again.</shortcut>
|
||||
<shortcut key="T">Inserts a new tunnel.</shortcut>
|
||||
<shortcut key="CTRL-N">New circuit.</shortcut>
|
||||
<shortcut key="CTRL-O">Open circuit.</shortcut>
|
||||
<shortcut key="CTRL-S">Save the circuit.</shortcut>
|
||||
<shortcut key="CTRL-Z">Undo last modification.</shortcut>
|
||||
<shortcut key="CTRL-Y">Redo the last undone modification.</shortcut>
|
||||
<shortcut key="P">Programs a diode or a FG-FET.</shortcut>
|
||||
<shortcut key="D">While drawing a wire switches to the diagonal mode.</shortcut>
|
||||
<shortcut key="F">While drawing a line flips the orientation.</shortcut>
|
||||
<shortcut key="S">Splits a single wire into two wires.</shortcut>
|
||||
<shortcut key="ESC">Abort the current action.</shortcut>
|
||||
<shortcut key="Del">Removes the selected components.</shortcut>
|
||||
<shortcut key="Backspace">Removes the selected components.</shortcut>
|
||||
<shortcut key="+">Increases the number of inputs at the component the mouse points to. If it is used with
|
||||
constants, the value is increased.
|
||||
</shortcut>
|
||||
<shortcut key="-">Decreases the number of inputs at the component the mouse points to. If it is used with
|
||||
constants, the value is decreased.
|
||||
</shortcut>
|
||||
<shortcut key="CTRL +">Zoom In</shortcut>
|
||||
<shortcut key="CTRL -">Zoom Out</shortcut>
|
||||
<shortcut key="F1">Fit to size</shortcut>
|
||||
<shortcut key="F5">Show or hide the components tree view</shortcut>
|
||||
</shortcuts>
|
||||
</chapter>
|
||||
</root>
|
||||
Loading…
x
Reference in New Issue
Block a user