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adds some test cases

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hneemann 2021-08-30 13:13:11 +02:00
parent 4b80369eef
commit c0a77228c8
4 changed files with 176 additions and 9 deletions
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40
src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java
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@ -136,15 +136,39 @@ public class VerilogGeneratorTest extends TestCase {
+ " assign s0 = inst[8];\n"
+ " assign \\9SD [7:0] = inst[7:0];\n"
+ " assign \\9SD [8] = s0;\n"
+ " assign \\9SD [9] = s0;\n"
+ " assign \\9SD [10] = s0;\n"
+ " assign \\9SD [11] = s0;\n"
+ " assign \\9SD [12] = s0;\n"
+ " assign \\9SD [13] = s0;\n"
+ " assign \\9SD [14] = s0;\n"
+ " assign \\9SD [15] = s0;\n"
+ "endmodule\n", out.toString());
+ " assign \\9SD [9] = s0;\n"
+ " assign \\9SD [10] = s0;\n"
+ " assign \\9SD [11] = s0;\n"
+ " assign \\9SD [12] = s0;\n"
+ " assign \\9SD [13] = s0;\n"
+ " assign \\9SD [14] = s0;\n"
+ " assign \\9SD [15] = s0;\n"
+ "endmodule\n", out.toString());
}
public void testSkip() throws Exception {
ToBreakRunner br = new ToBreakRunner("dig/hdl_skip/skipOuter.dig");
CodePrinterStr out = new CodePrinterStr();
new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
assertEquals("/*\n" +
" * Generated by Digital. Don't modify this file!\n" +
" * Any changes will be lost if this file is regenerated.\n" +
" */\n" +
"\n" +
"module skipOuter (\n" +
" input A,\n" +
" input B,\n" +
" output Y\n" +
");\n" +
" wire s0;\n" +
" skipInner skipInner_i0 (\n" +
" .i( B ),\n" +
" .o( s0 )\n" +
" );\n" +
" assign Y = (A & s0);\n" +
"endmodule\n", out.toString());
}
}

31
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
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@ -169,8 +169,37 @@ public class VHDLGeneratorTest extends TestCase {
" n9SD(13) <= s0;\n" +
" n9SD(14) <= s0;\n" +
" n9SD(15) <= s0;\n" +
"end Behavioral;\n",out.toString());
"end Behavioral;\n", out.toString());
}
public void testSkip() throws Exception {
ToBreakRunner br = new ToBreakRunner("dig/hdl_skip/skipOuter.dig");
CodePrinterStr out = new CodePrinterStr();
new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
assertEquals("-- generated by Digital. Don't modify this file!\n" +
"-- Any changes will be lost if this file is regenerated.\n" +
"\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"\n" +
"entity main is\n" +
" port (\n" +
" A: in std_logic;\n" +
" B: in std_logic;\n" +
" Y: out std_logic);\n" +
"end main;\n" +
"\n" +
"architecture Behavioral of main is\n" +
" signal s0: std_logic;\n" +
"begin\n" +
" gate0: entity work.skipInner\n" +
" port map (\n" +
" i => B,\n" +
" o => s0);\n" +
" Y <= (A AND s0);\n" +
"end Behavioral;\n", out.toString());
}
}

48
src/test/resources/dig/hdl_skip/skipInner.dig Normal file
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@ -0,0 +1,48 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes>
<entry>
<string>skipHDL</string>
<boolean>true</boolean>
</entry>
</attributes>
<visualElements>
<visualElement>
<elementName>Not</elementName>
<elementAttributes/>
<pos x="420" y="260"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>o</string>
</entry>
</elementAttributes>
<pos x="480" y="260"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>i</string>
</entry>
</elementAttributes>
<pos x="400" y="260"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="460" y="260"/>
<p2 x="480" y="260"/>
</wire>
<wire>
<p1 x="400" y="260"/>
<p2 x="420" y="260"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>

66
src/test/resources/dig/hdl_skip/skipOuter.dig Normal file
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@ -0,0 +1,66 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Y</string>
</entry>
</elementAttributes>
<pos x="580" y="260"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>A</string>
</entry>
</elementAttributes>
<pos x="400" y="240"/>
</visualElement>
<visualElement>
<elementName>And</elementName>
<elementAttributes/>
<pos x="500" y="240"/>
</visualElement>
<visualElement>
<elementName>skipInner.dig</elementName>
<elementAttributes/>
<pos x="420" y="280"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>B</string>
</entry>
</elementAttributes>
<pos x="400" y="280"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="400" y="240"/>
<p2 x="500" y="240"/>
</wire>
<wire>
<p1 x="560" y="260"/>
<p2 x="580" y="260"/>
</wire>
<wire>
<p1 x="480" y="280"/>
<p2 x="500" y="280"/>
</wire>
<wire>
<p1 x="400" y="280"/>
<p2 x="420" y="280"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>