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added Verilog LookUpTable template

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hneemann 2019-03-01 19:19:20 +01:00
parent 3833ae966a
commit c114f7954b
2 changed files with 50 additions and 5 deletions
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36
src/main/resources/verilog/DIG_LookUpTable.v Normal file
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@ -0,0 +1,36 @@
<?
if (elem.Label="")
panic("err_lutNeedsALabelToBeExported");
lutSize := 1 << elem.Inputs;
moduleName = format("LUT_%s", elem.Label);
dBitRange := format("[%d:0]", elem.Bits - 1);
?>module <?= moduleName ?> (
<?- for (i:=0;i<elem.Inputs;i++) {?>
input \<?=i?> ,
<?- }?>
output reg <?= dBitRange ?> out
);
reg <?= dBitRange ?> my_lut [0:<?= (lutSize - 1) ?>];
wire [<?=elem.Inputs-1?>:0] temp;
assign temp = {<?
for (i:=elem.Inputs-1;i>=0;i--) {
if (i<elem.Inputs-1) {
print(" , ");
}
print("\\"+i);
}
?> };
always @ (*) begin
out = my_lut[temp];
end
initial begin<?
for (i := 0; i < lutSize; i++) { ?>
my_lut[<?= i ?>] = <?= format("%d'h%x", elem.Bits, elem.Data[i]) ?>;<?
} ?>
end
endmodule

19
src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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@ -19,20 +19,19 @@ import de.neemann.digital.integration.Resources;
import de.neemann.digital.integration.TestExamples;
import de.neemann.digital.integration.ToBreakRunner;
import junit.framework.TestCase;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
import java.io.File;
import java.io.IOException;
import java.nio.file.Files;
import java.nio.file.Path;
import java.nio.file.Paths;
import java.text.DateFormat;
import java.text.SimpleDateFormat;
import java.util.ArrayList;
import java.util.Date;
import java.nio.file.Path;
import java.nio.file.Paths;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
public class VerilogSimulatorTest extends TestCase {
private static final Logger LOGGER = LoggerFactory.getLogger(VerilogSimulatorTest.class);
private static String IVERILOG = System.getProperty("iverilog", "");
@ -41,6 +40,16 @@ public class VerilogSimulatorTest extends TestCase {
private static final boolean foundIVerilog = findIVerilogDir();
private int testBenches;
/*
public void testDebug() throws Exception {
File file = new File(Resources.getRoot(), "dig/test/vhdl/lut.dig");
ToBreakRunner br = new ToBreakRunner(file);
System.out.println(new VerilogGenerator(br.getLibrary(), new CodePrinterStr(true)).export(br.getCircuit()));
checkVerilogExport(file);
}*/
public void testInSimulator() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {