TheCloud/Digital
1
0
Fork 0
mirror of https://github.com/hneemann/Digital.git synced 2025-09-13 23:06:22 -04:00
Code Issues Packages Projects Releases Wiki Activity

Comparator template uses new whitespace control.

Browse Source
This commit is contained in:
hneemann 2018-03-23 08:42:35 +01:00
parent 3be8e0664c
commit c2e58b64a4
5 changed files with 25 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/java/de/neemann/digital/hdl/hgs/Parser.java
View File

@ -173,8 +173,11 @@ public class Parser {
throw newUnexpectedToken(refToken);
}
case CODEEND:
final String str = tok.readText();
return c -> c.print(str);
String str = tok.readText();
if (nextIs(SUB))
str = Value.trimRight(str);
final String strc = str;
return c -> c.print(strc);
case SUB:
expect(CODEEND);
final String strt = Value.trimLeft(tok.readText());

2
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
View File

@ -99,7 +99,7 @@ public class VHDLTemplate implements VHDLEntity {
try {
String port = getEntity(node).getPortDecl();
if (port != null) {
out.dec().print(port).inc();
out.dec().print(Value.trimRight(port)).println().inc();
} else {
out.println("port (").inc();
Separator semic = new Separator(";\n");

20
src/main/resources/vhdl/DIG_Comparator.tem
View File

@ -1,16 +1,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
<?-
if (elem.Signed) {
entityName:="COMP_GATE_SIGNED";
print("USE ieee.numeric_std.all;");
print("\nUSE ieee.numeric_std.all;");
} else
entityName:="COMP_GATE_UNSIGNED";
?>
entity <?=entityName?> is
<? vhdl.beginGenericPort();?>
<?- vhdl.beginGenericPort();?>
generic ( Bits : integer );<? vhdl.registerGeneric("Bits");?>
port (
PORT_gr: out std_logic;
@ -18,26 +18,26 @@ entity <?=entityName?> is
PORT_le: out std_logic;
PORT_a: in <?= vhdl.genericType(elem.Bits)?>;
PORT_b: in <?= vhdl.genericType(elem.Bits)?> );
<? vhdl.endGenericPort();?>
<?- vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
process(PORT_a,PORT_b)
begin
<? if (elem.Signed) { ?>
<?- if (elem.Signed) { ?>
if (signed(PORT_a) > signed(PORT_b)) then
<? } else { ?>
<?- } else { ?>
if (PORT_a > PORT_b ) then
<? } ?>
<?- } ?>
PORT_le <= '0';
PORT_eq <= '0';
PORT_gr <= '1';
<? if (elem.Signed) { ?>
<?- if (elem.Signed) { ?>
elsif (signed(PORT_a) < signed(PORT_b)) then
<? } else { ?>
<?- } else { ?>
elsif (PORT_a < PORT_b) then
<? } ?>
<?- } ?>
PORT_le <= '1';
PORT_eq <= '0';
PORT_gr <= '0';

7
src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
View File

@ -500,6 +500,13 @@ public class ParserTest extends TestCase {
assertEquals("5 ", exec(" <?-=5?> ").toString());
assertEquals("5", exec("\n\n <?-=5;-?>\n\n").toString());
assertEquals("\n 5 \n", exec("\n <?=5?> \n").toString());
assertEquals("5", exec("\n\n <?- print(5);-?>\n\n").toString());
assertEquals(" 5", exec("<??> <?=5;-?> ").toString());
assertEquals("5 ", exec("<??> <?-=5?> ").toString());
assertEquals("5", exec("<??>\n\n <?-=5;-?>\n\n").toString());
assertEquals("\n 5 \n", exec("<??>\n <?=5?> \n").toString());
assertEquals("5", exec("<??>\n\n <?- print(5);-?>\n\n").toString());
}
// checks the available VHDL templates

4
src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java
View File

@ -39,14 +39,14 @@ public class VHDLFileTest extends TestCase {
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic;\n" +
" PORT_notQ : out std_logic );\n" +
" end component;\n" +
" end component;\n" +
" component DIG_D_FF_BUS\n" +
" generic ( Bits: integer ); \n" +
" port ( PORT_D : in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_notQ : out std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
" signal S1: std_logic;\n" +
" signal S2: std_logic_vector (2 downto 0);\n" +