minor improvement of verilog identifier renaming, closes #582

This commit is contained in:
hneemann 2020-12-20 10:19:48 +01:00
parent 4efe6e4c88
commit d03cc1c492
3 changed files with 13 additions and 8 deletions

View File

@ -6,8 +6,8 @@
package de.neemann.digital.hdl.verilog2;
import de.neemann.digital.hdl.model2.HDLModel;
import java.util.Arrays;
import java.util.Arrays;
import java.util.HashSet;
/**
@ -38,17 +38,16 @@ public class VerilogRenaming implements HDLModel.Renaming {
if (isKeyword(name) || !isFirstCharValid(name))
// Escaped identifier, the space is part of the identifier.
return "\\" + name + " ";
else {
else
return cleanName(name);
}
}
private boolean isFirstCharValid(String name) {
char c = name.charAt(0);
return ((c >= 'a' && c <= 'z')
|| (c >= 'A' && c <= 'Z')
|| (c == '_'));
|| (c >= 'A' && c <= 'Z')
|| (c == '_'));
}
private boolean isKeyword(String str) {
@ -62,12 +61,14 @@ public class VerilogRenaming implements HDLModel.Renaming {
for (int i = 0; i < name.length(); i++) {
char c = name.charAt(i);
if ((c >= 'a' && c <= 'z')
|| (c >= 'A' && c <= 'Z')
|| (c >= '0' && c <= '9')
|| (c == '_') || (c == '$'))
|| (c >= 'A' && c <= 'Z')
|| (c >= '0' && c <= '9')
|| (c == '_') || (c == '$'))
sb.append(c);
else {
switch (c) {
case '\\':
break;
case '/':
case '!':
case '~':

View File

@ -25,5 +25,7 @@ public class VerilogRenamingTest extends TestCase {
assertEquals("\\a<b ", r.checkName("a<b"));
assertEquals("\\a>b ", r.checkName("a>b"));
assertEquals("\\a=b ", r.checkName("a=b"));
assertEquals("a_b", r.checkName("a\\_b"));
assertEquals("\\a^b ", r.checkName("a\\^b"));
}
}

View File

@ -25,5 +25,7 @@ public class VHDLRenamingTest extends TestCase {
assertEquals("aleb", r.checkName("a<b"));
assertEquals("agrb", r.checkName("a>b"));
assertEquals("aeqb", r.checkName("a=b"));
assertEquals("a_b", r.checkName("a\\_b"));
assertEquals("a_b", r.checkName("a\\^b"));
}
}