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adds hdl support for the NEG component

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This commit is contained in:
hneemann 2020-08-26 09:47:25 +02:00
parent 07c93bf325
commit d58b7cf1a7
6 changed files with 116 additions and 6 deletions
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12
src/main/resources/verilog/DIG_Neg.v Normal file
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@ -0,0 +1,12 @@
<?
generics[0] := "Bits";
?>
module DIG_Neg #(
parameter Bits = 1
)
(
input signed [(Bits-1):0] in,
output signed [(Bits-1):0] out
);
assign out = -in;
endmodule

15
src/main/resources/vhdl/DIG_Neg.tem Normal file
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@ -0,0 +1,15 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_Neg is
generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
port (
p_in: in std_logic_vector ((Bits-1) downto 0);
p_out: out std_logic_vector ((Bits-1) downto 0) );
end DIG_Neg;
architecture Behavioral of DIG_Neg is
begin
p_out <= std_logic_vector(-signed(p_in));
end Behavioral;

4
src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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@ -51,8 +51,8 @@ public class VerilogSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
assertEquals(57, tested);
assertEquals(51, testBenches);
assertEquals(58, tested);
assertEquals(52, testBenches);
} catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok
}

4
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
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@ -43,8 +43,8 @@ public class VHDLSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
assertEquals(57, tested);
assertEquals(51, testBenches);
assertEquals(58, tested);
assertEquals(52, testBenches);
} catch (FileScanner.SkipAllException e) {
// if ghdl is not installed its also ok
}

4
src/test/java/de/neemann/digital/integration/TestExamples.java
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@ -44,8 +44,8 @@ public class TestExamples extends TestCase {
*/
public void testTestExamples() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test");
assertEquals(192, new FileScanner(this::check).scan(examples));
assertEquals(181, testCasesInFiles);
assertEquals(193, new FileScanner(this::check).scan(examples));
assertEquals(182, testCasesInFiles);
}
/**

83
src/test/resources/dig/test/vhdl/neg.dig Normal file
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@ -0,0 +1,83 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>a</string>
</entry>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
<entry>
<string>intFormat</string>
<intFormat>decSigned</intFormat>
</entry>
</elementAttributes>
<pos x="360" y="200"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>a y
0 0
1 15
2 14
14 2
15 1
8 8</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="360" y="240"/>
</visualElement>
<visualElement>
<elementName>Neg</elementName>
<elementAttributes>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="380" y="200"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>y</string>
</entry>
<entry>
<string>intFormat</string>
<intFormat>decSigned</intFormat>
</entry>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="460" y="200"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="360" y="200"/>
<p2 x="380" y="200"/>
</wire>
<wire>
<p1 x="440" y="200"/>
<p2 x="460" y="200"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>