updated the documentation.

src/test/java/de/neemann/digital/toolchain/BASYS3Test.java

@@ -20,11 +20,11 @@ import java.io.IOException;
 public class BASYS3Test extends TestCase {
 
     public void testMMCME2_BASEParams() throws IOException, ParserException, HGSEvalException {
-        Configuration c = Configuration.load(new File(Resources.getRoot(), "../../main/dig/hdl/BASYS3_Config.xml"));
+        Configuration c = Configuration.load(new File(Resources.getRoot(), "../../main/dig/hdl/BASYS3.config"));
         FileToCreate clock = c.getFileById("MMCME2_BASE",null);
 
         String content = clock.getContent();
-        for (int f = 5000; f < 500000; f+=77) {
+        for (int f = 4688; f < 500000; f+=77) {
             Context context = new Context().disableLogging();
             context.declareVar("hdl",
                     new ElementAttributes()

src/test/resources/docu/static_de.xml

@@ -393,7 +393,7 @@
             </par>
             <par>
                 Beim BASYS3 Board wird, wenn die Taktfrequenz niedrig ist, ein Frequenzteiler in den HDL Code integriert,
-                um den Boardtakt entsprechend zu teilen. Wenn die in der Schaltung gewählte Taktfrequenz über 37kHz
+                um den Boardtakt entsprechend zu teilen. Wenn die in der Schaltung gewählte Taktfrequenz über 4.7MHz
                 liegt, wird die MMCM Einheit des Artix-7 zur Takterzeugung verwendet.
                 Dies stellt sicher, dass die für die Taktverteilung vorgesehenen FPGA-Resourcen auch tatsächlich
                 verwendet werden.
@@ -409,8 +409,10 @@
                 Hardware-Manager kann dieser in ein BASYS3 Board übertragen werden.
             </par>
             <par>
-                Um neben der HDL Datei auch die erforderliche Constraints-Datei erzeugen zu lassen, muss die Schaltung
+                Um neben der HDL Datei auch die erforderliche Constraints-Datei erzeugen zu lassen, muss in den
-                ein Textfeld mit dem Text "Board: BASYS3", "Board: MimasV1" oder "Board: MimasV2" enthalten.
+                Einstellungen das Entsprechende Board konfiguriert werden. Dazu kann im Feld "Toolchain Konfiguration"
+                die entspechende XML-Datei ausgewählt werden. Die verfügbaren Konfgurationen finden sich im Ordner
+                <e>examples/hdl</e> und haben die Dateiendung <e>.config</e>.
             </par>
         </subchapter>
     </chapter>

src/test/resources/docu/static_en.xml

@@ -367,7 +367,7 @@
             <par>
                 At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL
                 code to divide the board clock accordingly.
-                If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the
+                If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the
                 Artix-7 is used for clock generation.
                 This ensures that the FPGA resources provided for the clock distribution are used.
                 This allows the included example processor to run at 20MHz, and if you can do without the
@@ -383,8 +383,11 @@
                 to program a BASYS3 board.
             </par>
             <par>
-                To create the required constraints file, the circuit must contain a text field with the text
+                In order to create the required constraints file in addition to the HDL file, the corresponding board
-                "Board: BASYS3", "Board: MimasV1" or "Board: MimasV2".
+                must be configured in the settings. In the field "Toolchain Configuration" the corresponding XML file
+                can be selected.
+                The available configurations can be found in the folder <e>examples/hdl</e> and have the file
+                extension <e>.config</e>.
             </par>
         </subchapter>
     </chapter>

src/test/resources/docu/static_es.xml

@@ -307,7 +307,7 @@
             </par>
             <par>
                 En la placa BASYS3, si la frecuencia del reloj del circuito es baja, se integrará en el código HDL un divisor de frecuencia para dividir la frecuencia de la placa adecuadamente.
-				Si la frecuencia de reloj seleccionada supera los 37 kHz, la unidad MMCM de la Artix-7 se empleará para la generación del reloj
+				Si la frecuencia de reloj seleccionada supera los 4.7MHz, la unidad MMCM de la Artix-7 se empleará para la generación del reloj
 				Esto asegura que los recursos de la FPGA proporcionados por la distribución del reloj se emplean.
 				Esto permite al procesador incluido correr a 20 MHz y si sabe hacerlo sin el multiplicador, es posible hacerlo a 30 MHz.
             </par>

src/test/resources/docu/static_es_ref.xml

@@ -367,7 +367,7 @@
             <par>
                 At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL
                 code to divide the board clock accordingly.
-                If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the
+                If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the
                 Artix-7 is used for clock generation.
                 This ensures that the FPGA resources provided for the clock distribution are used.
                 This allows the included example processor to run at 20MHz, and if you can do without the

src/test/resources/docu/static_pt.xml

@@ -364,7 +364,7 @@
             <par>
                 Na placa BASYS3, se a frequência de clock de um circuito for baixa, um divisor de frequências será incorporado ao código HDL
                 a fim de dividir o clock da placa para o valor conveniente.
-                Se a frequência de clock selecionada exceder 37kHz, a unidade MMCM do Artix-7 será usada para a geração de clock.
+                Se a frequência de clock selecionada exceder 4.7MHz, a unidade MMCM do Artix-7 será usada para a geração de clock.
                 Isso garantirá que os recursos disponíveis na FPGA para distribuição do clock serão usados.
                 Isso permitirá que o exemplo de processador possa ser executado a 20MHz, e se quiser, sem o multiplicador,
                 30HMz também será possível.

src/test/resources/docu/static_pt_ref.xml

@@ -367,7 +367,7 @@
             <par>
                 At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL
                 code to divide the board clock accordingly.
-                If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the
+                If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the
                 Artix-7 is used for clock generation.
                 This ensures that the FPGA resources provided for the clock distribution are used.
                 This allows the included example processor to run at 20MHz, and if you can do without the