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adds hdl templates for async ram

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This commit is contained in:
hneemann 2021-03-01 09:15:48 +01:00
parent 577de5f4ab
commit fae2890027
7 changed files with 191 additions and 7 deletions
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3
src/main/java/de/neemann/digital/core/memory/RAMAsync.java
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@ -33,7 +33,8 @@ public class RAMAsync extends Node implements Element, RAMInterface {
.addAttribute(Keys.ADDR_BITS)
.addAttribute(Keys.IS_PROGRAM_MEMORY)
.addAttribute(Keys.INVERTER_CONFIG)
.addAttribute(Keys.LABEL);
.addAttribute(Keys.LABEL)
.supportsHDL();
private final DataField memory;
private final ObservableValue output;

25
src/main/resources/verilog/DIG_RAMAsync.v Normal file
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@ -0,0 +1,25 @@
<?
// Module instantiation parameters
generics[0] := "Bits";
generics[1] := "AddrBits";
?>module <?= moduleName ?>
#(
parameter Bits = 8,
parameter AddrBits = 4
)
(
input [(AddrBits-1):0] A,
input [(Bits-1):0] D,
input we,
output [(Bits-1):0] Q
);
reg [(Bits-1):0] memory[0:((1 << AddrBits) - 1)];
assign Q = memory[A];
always @ (we, A, D) begin
if (we)
memory[A] <= D;
end
endmodule

28
src/main/resources/vhdl/DIG_RAMAsync.tem Normal file
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@ -0,0 +1,28 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_RAMAsync is
generic (
Bits : integer; <? vhdl.registerGeneric("Bits");?>
AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
port (
Q: out std_logic_vector ((Bits-1) downto 0);
A: in std_logic_vector ((AddrBits-1) downto 0);
D: in std_logic_vector ((Bits-1) downto 0);
we: in std_logic);
end DIG_RAMAsync;
architecture Behavioral of DIG_RAMAsync is
-- CAUTION: uses distributed RAM
type memoryType is array(0 to (2**AddrBits)-1) of STD_LOGIC_VECTOR((Bits-1) downto 0);
signal memory : memoryType;
begin
process ( we,A,D )
begin
if we='1' then
memory(to_integer(unsigned(A))) <= D;
end if;
end process;
Q <= memory(to_integer(unsigned(A)));
end Behavioral;

4
src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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@ -51,8 +51,8 @@ public class VerilogSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
assertEquals(67, tested);
assertEquals(57, testBenches);
assertEquals(68, tested);
assertEquals(58, testBenches);
} catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok
}

4
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
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@ -43,8 +43,8 @@ public class VHDLSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
assertEquals(67, tested);
assertEquals(57, testBenches);
assertEquals(68, tested);
assertEquals(58, testBenches);
} catch (FileScanner.SkipAllException e) {
// if ghdl is not installed its also ok
}

4
src/test/java/de/neemann/digital/integration/TestExamples.java
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@ -51,8 +51,8 @@ public class TestExamples extends TestCase {
*/
public void testTestExamples() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test");
assertEquals(208, new FileScanner(this::check).scan(examples));
assertEquals(193, testCasesInFiles);
assertEquals(209, new FileScanner(this::check).scan(examples));
assertEquals(194, testCasesInFiles);
}
/**

130
src/test/resources/dig/test/vhdl/ram/RAMAsync.dig Normal file
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@ -0,0 +1,130 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>A</string>
</entry>
<entry>
<string>Bits</string>
<int>8</int>
</entry>
</elementAttributes>
<pos x="360" y="220"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>we</string>
</entry>
</elementAttributes>
<pos x="360" y="320"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>D</string>
</entry>
<entry>
<string>Bits</string>
<int>8</int>
</entry>
</elementAttributes>
<pos x="360" y="280"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Q</string>
</entry>
<entry>
<string>Bits</string>
<int>8</int>
</entry>
</elementAttributes>
<pos x="520" y="280"/>
</visualElement>
<visualElement>
<elementName>RAMAsync</elementName>
<elementAttributes>
<entry>
<string>AddrBits</string>
<int>8</int>
</entry>
<entry>
<string>Bits</string>
<int>8</int>
</entry>
</elementAttributes>
<pos x="440" y="260"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>we A D Q
loop(n,256)
1 (n) (n) (n)
end loop
loop(n,256)
0 (n) 0 (n)
end loop
loop(n,256)
0 (n) 0 (n)
end loop
</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="440" y="180"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="360" y="320"/>
<p2 x="380" y="320"/>
</wire>
<wire>
<p1 x="380" y="260"/>
<p2 x="440" y="260"/>
</wire>
<wire>
<p1 x="360" y="280"/>
<p2 x="440" y="280"/>
</wire>
<wire>
<p1 x="500" y="280"/>
<p2 x="520" y="280"/>
</wire>
<wire>
<p1 x="380" y="300"/>
<p2 x="440" y="300"/>
</wire>
<wire>
<p1 x="360" y="220"/>
<p2 x="380" y="220"/>
</wire>
<wire>
<p1 x="380" y="300"/>
<p2 x="380" y="320"/>
</wire>
<wire>
<p1 x="380" y="220"/>
<p2 x="380" y="260"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>