hneemann
5871b672d3
closes #163
2018-06-17 14:17:07 +02:00
hneemann
7d7a34d350
closes #161
2018-06-14 11:17:58 +02:00
hneemann
3e03dd6d1e
updated the release notes
2018-06-14 08:56:54 +02:00
hneemann
d06f69e1f9
Merge branch 'verilog'
2018-06-11 16:44:06 +02:00
hneemann
814c703a9e
updated the release notes
2018-06-11 16:43:21 +02:00
hneemann
04b0fd04f4
updated the documentation
2018-06-11 16:18:00 +02:00
hneemann
6dfcd8af2f
typo
2018-06-10 15:37:41 +02:00
hneemann
86bea78e11
typo
2018-06-10 10:54:56 +02:00
hneemann
0a2d60420b
updated the readme
2018-06-10 10:47:16 +02:00
hneemann
8a0e3dede4
added export of verilog defined components to verilog.
2018-06-10 10:35:32 +02:00
hneemann
19193e96ec
added orientation attribute to text element, closes #159
2018-06-08 08:39:23 +02:00
hneemann
7021b9d574
Merge branch 'master' of github.com:ideras/Digital into verilog
2018-06-08 07:54:30 +02:00
hneemann
0f338cdecb
added rotation attribute to text element, see #159
2018-06-08 07:50:46 +02:00
Ivan de Jesus Deras
922a09eef7
Fixed a problem with the generated verilog code for the ROM component
2018-06-07 14:28:06 -06:00
Ivan de Jesus Deras
9af27c79cd
Changed the name of the IVerilog path key name
2018-06-06 16:00:16 -06:00
hneemann
89b0df3f13
Merge branch 'master' of github.com:ideras/Digital into verilog
...
# Merge erforderlich ist, insbesondere wenn es einen aktualisierten
# Upstream-Branch mit einem Thema-Branch zusammenführt.
#
# Zeilen beginnend mit '#' werden ignoriert, und eine leere Beschreibung
# bricht den Commit ab.
2018-06-06 19:06:56 +02:00
Ivan de Jesus Deras
5ae8ea73de
Added Icarus verilog path to the settings dialog
2018-06-05 16:46:30 -06:00
Ivan de Jesus Deras
61280d3db1
Added a test for Xilinx ISE Project generator
2018-06-05 16:26:53 -06:00
Ivan de Jesus Deras
7018f29e6b
Added a basic Spartan6 clock integrator using the DCM_SP primitive. Reorganize Boards code into one package
2018-06-05 10:44:57 -06:00
hneemann
302e925a24
typo
2018-06-02 15:09:39 +02:00
hneemann
39207fbba6
Added CodeCov icon to README.md
2018-06-02 11:49:27 +02:00
hneemann
0d47619fbf
Added CodeCov icon to README.md
2018-06-02 11:37:08 +02:00
hneemann
56d5a45b48
Added a GUI test for the TestAllDialog.
2018-06-02 11:27:25 +02:00
hneemann
81e41a973c
Refactoring of TestAllDialog
2018-06-01 23:09:34 +02:00
hneemann
9c781d0731
Added jacoco and codecov to the build process.
2018-06-01 21:38:26 +02:00
Ivan de Jesus Deras
ee77b2f334
Removed unused class Token
2018-06-01 13:05:43 -06:00
hneemann
92c32ac118
Merge branch 'keyAccessError'
2018-06-01 20:15:37 +02:00
Ivan de Jesus Deras
314fd7121d
Generate a table driven verilog test benches, which result in faster execution of the test.
2018-06-01 11:35:17 -06:00
hneemann
c476bb923e
Adds a "test all" function.
2018-06-01 19:32:22 +02:00
Ivan de Jesus Deras
9eec5e25a7
Committing missing changes from last commit. Arggg
2018-06-01 11:30:28 -06:00
Ivan de Jesus Deras
e0ceb49a1b
Added support for verilog to the external component. This makes possible to use verilog to define the behaviour of a component
2018-06-01 11:26:21 -06:00
hneemann
ac063e2bd6
limits the menu size in the component menu. Closes #152
2018-05-31 16:16:52 +02:00
hneemann
aa207fb8ce
Fixes some issues concerning a not working undo. See #155
2018-05-31 15:35:11 +02:00
hneemann
cf124cfd16
fixes a NullPointer
2018-05-31 14:01:53 +02:00
hneemann
eb5cf1e254
Measurement graph omits the line if in high-z state. Closes #154
2018-05-31 13:07:04 +02:00
Ivan de Jesus Deras
059252ee5b
Added missing files from last commit
2018-05-24 21:31:06 -06:00
Ivan de Jesus Deras
67a2a4f941
Added support for MimasV1 & MimasV2 Spartan6 FPGA Boards. Now it's possible to generate a Xilinx ISE project file
2018-05-24 21:28:39 -06:00
Ivan de Jesus Deras
2f134477d5
Updated the verilog exporter to use the new HGS template engine and the
...
new HDLModel
2018-05-24 16:16:00 -06:00
hneemann
808a50712e
added some comments
2018-05-24 10:27:28 +02:00
hneemann
5c84d30f84
added some comments
2018-05-24 08:35:54 +02:00
hneemann
b91086a661
don't look for new releases if a pre release build is used.
2018-05-22 12:19:29 +02:00
hneemann
bf72a3dd34
prepared renaming
2018-05-21 10:00:58 +02:00
Ivan de Jesus Deras
aec926d9bd
Changed the verilog templates to use the HGS engine
2018-05-20 18:42:10 -06:00
hneemann
9d4da20a48
added some comments
2018-05-20 14:55:46 +02:00
hneemann
646d3854d0
renamed a constant
2018-05-20 11:58:02 +02:00
hneemann
e7a75fb45c
fixed a screenshot
2018-05-19 20:47:34 +02:00
Ivan de Jesus Deras
76ee11f6f9
Merge remote-tracking branch 'upstream/master'
2018-05-19 06:34:39 -06:00
hneemann
ebc596e3f6
Added a tabbed pane to the attributes dialog to make it more beginner friendly.
2018-05-19 12:49:56 +02:00
hneemann
28db768c8e
Allows selection of the shape displayed when a DIL chip is used. Closes #147
...
Squashed commit of the following:
commit 57aa3e06cf2442a1100963d8b22857be1e5e56c3
Author: hneemann <helmut.neemann@arcor.de>
Date: Sat May 19 08:54:45 2018 +0200
minor refactoring
commit e8eaa0656d21f451fd433d57ea6a9c40a4ef4b16
Author: hneemann <helmut.neemann@arcor.de>
Date: Fri May 18 21:05:05 2018 +0200
show "use default shape" attribute only if necessary
commit 8c1b0a8f54de83b88c465a8ec5e89b8230bccf88
Author: hneemann <helmut.neemann@arcor.de>
Date: Fri May 18 20:46:13 2018 +0200
minor refactorings
commit f0f32ae0badde2279fe5a74d9435a0a39086b5c4
Author: hneemann <helmut.neemann@arcor.de>
Date: Fri May 18 19:13:17 2018 +0200
another correction of the dil shape size
commit 06cb4b4c8d7e80404fa82f82906b1bd3fcb80d27
Author: hneemann <helmut.neemann@arcor.de>
Date: Thu May 17 18:57:50 2018 +0200
Allows to show default shape also if DIL shape is selected in the circuit.
2018-05-19 09:09:01 +02:00
hneemann
9db6bcba03
optimized test imports
2018-05-15 20:55:35 +02:00
