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Add minimal insn descriptions to the Instruction Encoding Formats section.
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John Winans
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@ -1,3 +1,6 @@
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\newcommand\instructionHeader[1]{{\large\tt \string#1}}
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\chapter{RV32 Machine Instructions}
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\label{chapter:RV32}
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\index{RV32}
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@ -247,26 +250,30 @@ immediate, register, base-displacement, pc-relative
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Instruction Encoding Formats}
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\label{section:EncodingFormats}
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This
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\enote{Should discuss types and sizes beyond the fundamentals. Will add
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if/when instruction details are added in the future.}
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document concerns itself with the following RISC-V instruction formats.
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XXX Show and discuss a stack of formats explaining how the unnatural ordering
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of the {\em imm} fields reduces the number of possible locations that
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the hardware has to be prepared to {\em look} for various bits. For example,
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the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always
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in the same position. Also note that imm[19:12] and imm[10:5] can only be
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found in one place. imm[4:0] can only be found in one of two places\ldots
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%XXX Show and discuss a stack of formats explaining how the unnatural ordering
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%of the {\em imm} fields reduces the number of possible locations that
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%the hardware has to be prepared to {\em look} for various bits. For example,
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%the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always
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%in the same position. Also note that imm[19:12] and imm[10:5] can only be
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%found in one place. imm[4:0] can only be found in one of two places\ldots
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The point to all this is that it is easier to build a machine if it
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does not have to accommodate many different ways to perform the same task.
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This simplification can also allow it operate faster.
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The method/format of an instruction is designed with an eye on the ease
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of future manufacture of the machine that will execute them. It is
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easier to build a machine if it does not have to accommodate many different
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ways to perform the same task. The result is that a machine can be
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built with fewer gates, consumes less power, and can run faster than
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if it were built when a priority is on how a user might prefer to decode
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the same instructions from a hex dump.
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\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats.
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This document concerns itself with the RISC-V instruction formats shown
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in \autoref{Figure:riscvFormats}.
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%\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats.
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\begin{figure}[ht]
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\DrawInsnTypeBTikz{00000000000000000000000000000000}\\
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@ -280,6 +287,9 @@ This simplification can also allow it operate faster.
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\label{Figure:riscvFormats}
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\end{figure}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{U Type}
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\label{insnformat:utype}
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@ -319,13 +329,39 @@ value suggests a rationale for the name of this format.
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%from $01010110000000000011_2$ (\verb@d6003@$_{16}$) to
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%$11010110000000000011000000000000_2$ (\verb@d6003000@$_{16}$).
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If \Gls{xlen}=64 then the imm value in this example will be converted to the
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same two's complement integer value by extending the sign to the left.
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%\DrawBitBoxSignLeftZeroRightExtendedPicture{64}{11010110000000000011}{12}
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%$1111111111111111111111111111111111010110000000000011000000000000_2$
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%(\verb@ffffffffd6003000@$_{16}$).
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\begin{itemize}
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\item\instructionHeader{lui\ \ \ rd,imm}
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\label{insn:lui}
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Set register \verb@rd@ to the \verb@imm_u@ value as shown in \autoref{Figure:u_type_decode}.
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For example: \verb@lui x23,0x12345@ will result in setting register \verb@x23@ to
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the value \verb@0x12335000@.
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\item\instructionHeader{auipc rd,imm}
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\label{insn:auipc}
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Add the address of the instruction to the \verb@imm_u@ value as
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shown \autoref{Figure:u_type_decode} and store the result in register \verb@rd@.
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For example, if the instruction \verb@auipc x22,0x10001@ is executed from
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memory address \verb@0x800012f4@ then register \verb@x22@ will be set to
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\verb@0x900022f4@.
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\end{itemize}
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If \Gls{xlen}=64 then the \verb@imm_u@ value in this example will be converted to the
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same two's complement integer value by extending the sign-bit (indicated by \verb@a@
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in \autoref{Figure:u_type_decode}) to the left.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{J Type}
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\label{insnformat:jtype}
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@ -393,14 +429,121 @@ counter. Since no instruction can be placed at an odd address the 20-bit
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imm value is zero-extended to the right to represent a 21-bit signed offset
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capable of representing numbers twice the magnitude of the 20-bit imm value.
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\begin{itemize}
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\item\instructionHeader{jal\ \ \ rd,imm}
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\label{insn:jal}
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Set register \verb@rd@ to the address of the next instruction that would
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otherwise be executed (the address of the \verb@jal@ instruction + 4) and then
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jump to an address given by the sum of the \verb@pc@ register and the
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\verb@imm_j@ value as decoded from the instruction shown in \autoref{imm.j:decode}.
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\end{itemize}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{R Type}
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\label{insnformat:rtype}
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\DrawInsnTypeRTikz{01000001111100011000001110110011}
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The R-type instructions are used for operations that set a destination
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register \verb@rd@ to the result of an arithmetic, logical or shift operation
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applied to source registers \verb@rs1@ and \verb@rs2@.
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Note that bit 30 is used to select between the \verb@add@ and \verb@sub@ instructions
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as well as to select between arithmetic and logical shifting.
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\begin{itemize}
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\item\instructionHeader{add\ \ \ rd,rs1,rs2}
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\label{insn:add}
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Set register \verb@rd@ to \verb@rs1 + rs2@.
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\item\instructionHeader{and\ \ \ rd,rs1,rs2}
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\label{insn:and}
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Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@rs2@.
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For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@
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then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0x55001100@.
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\item\instructionHeader{or\ \ \ \ rd,rs1,rs2}
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\label{insn:or}
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Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@rs2@.
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For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@
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then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0xff55ff11@.
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\item\instructionHeader{sll\ \ \ rd,rs1,rs2}
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\label{insn:sll}
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Shift \verb@rs1@ left by the number of bits given in \verb@rs2@ and
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store the result in \verb@rd@.
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For example, if \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x08@
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then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0x34567800@.
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\item\instructionHeader{slt\ \ \ rd,rs1,rs2}
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\label{insn:slt}
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If the signed integer value in \verb@rs1@ is less than the
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signed integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@.
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Otherwise, set \verb@rd@ to \verb@0@.
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\item\instructionHeader{sltu\ \ rd,rs1,rs2}
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\label{insn:sltu}
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If the unsigned integer value in \verb@rs1@ is less than the
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unsigned integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@.
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Otherwise, set \verb@rd@ to \verb@0@.
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\item\instructionHeader{sra\ \ \ rd,rs1,rs2}
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\label{insn:sra}
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Logic-shift \verb@rs1@ right by the number of bits given in \verb@rs2@ and
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store the result in \verb@rd@.
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For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@
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then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0xff876543@.
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\item\instructionHeader{srl\ \ \ rd,rs1,rs2}
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\label{insn:srl}
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Logic-shift \verb@rs1@ right by the number of bits given in \verb@rs2@ and
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store the result in \verb@rd@.
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For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@
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then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0x00876543@.
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\item\instructionHeader{sub\ \ \ rd,rs1,rs2}
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\label{insn:sub}
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Set register \verb@rd@ to \verb@rs1 - rs2@.
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\item\instructionHeader{xor\ \ \ rd,rs1,rs2}
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\label{insn:xor}
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Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@rs2@.
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For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@
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then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the
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value \verb@0xaa55ee11@.
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\end{itemize}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{I Type}
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\label{insnformat:itype}
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@ -419,7 +562,7 @@ and converted as shown in \autoref{Figure:i_type_decode}.
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\end{figure}
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A special case of the I-type used for shift-immediate instructions where
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the {\em imm} field is used as an immediate value named {\em shamt}
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the {\em imm} field is used as an immediate value named {\em shamt\_i}
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representing the number of bit positions to shift as shown in
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\autoref{Figure:shamt_i_type_decode}.
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@ -434,7 +577,184 @@ representing the number of bit positions to shift as shown in
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Note that bit 30 is used to select between arithmetic and logical shifting.
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%\DrawInsnTypeIShiftTikz{00000000001000011001001110100011}
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\begin{figure}[ht]
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\centering
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\begin{verbatim}
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00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*
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00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....*
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00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*
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00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*
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00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*
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\end{verbatim}
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\captionof{figure}{An Example Memory Dump.}
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\label{Figure:imm:memory:dump}
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\end{figure}
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\begin{itemize}
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\item\instructionHeader{addi\ \ rd,rs1,imm}
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\label{insn:addi}
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Set register \verb@rd@ to \verb@rs1 + imm_i@.
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\item\instructionHeader{andi\ \ rd,rs1,imm}
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\label{insn:andi}
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Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@imm_i@.
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For example, if \verb@x17@ = \verb@0x55551111@ then the instruction
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\verb@andi x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x00000011@.
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Recall that \verb@imm@ is sign-extended.
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Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction
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\verb@andi x12,x17,0x800@ will set \verb@x12@ to the value \verb@0x55551000@.
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\item\instructionHeader{jalr\ \ rd,rs1,imm}
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\label{insn:jalr}
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Set register \verb@rd@ to the address of the next instruction that would
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otherwise be executed (the address of the \verb@jalr@ instruction + 4) and then
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jump to an address given by the sum of the \verb@pc@ register and the
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\verb@imm_i@ value as decoded from the instruction shown in \autoref{imm.i:decode}.
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Note that the \verb@pc@ register can never refer to an odd address.
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This instruction will explicitly set the \acrshort{lsb} to zero regardless
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of the value of \verb@rs1@.
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\item\instructionHeader{lb\ \ \ \ rd,imm(rs1)}
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\label{insn:lb}
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Set register \verb@rd@ to the value of the sign-extended byte fetched from
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the memory address given by the sum of \verb@rs1@ and \verb@imm_i@.
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For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
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if register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lb x12,1(x13)@ will set \verb@x12@ to the value \verb@0xffffff80@.
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\item\instructionHeader{lbu\ \ \ rd,imm(rs1)}
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\label{insn:lbu}
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Set register \verb@rd@ to the value of the zero-extended byte fetched from
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the memory address given by the sum of \verb@rs1@ and \verb@imm_i@.
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For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
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if register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lb x12,1(x13)@ will set \verb@x12@ to the value \verb@0x00000080@.
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\item\instructionHeader{lh\ \ \ \ rd,imm(rs1)}
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\label{insn:lh}
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Set register \verb@rd@ to the value of the sign-extended 16-bit little-endian
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half-word value fetched from the memory address given by the sum
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of \verb@rs1@ and \verb@imm_i@.
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For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
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if register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lh x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@.
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If register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lh x12,-8(x13)@ will set \verb@x12@ to the value \verb@0xffff87b7@.
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\item\instructionHeader{lhu\ \ \ rd,imm(rs1)}
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\label{insn:lhu}
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Set register \verb@rd@ to the value of the zero-extended 16-bit little-endian
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half-word value fetched from the memory address given by the sum
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of \verb@rs1@ and \verb@imm_i@.
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For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
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if register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lhu x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@.
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If register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lhu x12,-8(x13)@ will set \verb@x12@ to the value \verb@0x000087b7@.
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\item\instructionHeader{lw\ \ \ \ rd,imm(rs1)}
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\label{insn:lw}
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Set register \verb@rd@ to the value of the sign-extended 32-bit little-endian
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word value fetched from the memory address given by the sum
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of \verb@rs1@ and \verb@imm_i@.
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For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
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if register \verb@x13@ = \verb@0x00002650@ then the instruction
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\verb@lh x12,-4(x13)@ will set \verb@x12@ to the value \verb@4307a503@.
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\item\instructionHeader{ori\ \ \ rd,rs1,imm}
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\label{insn:ori}
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Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@imm_i@.
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For example, if \verb@x17@ = \verb@0x55551111@ then the instruction
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\verb@ori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ff@.
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Recall that \verb@imm@ is sign-extended.
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Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction
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\verb@ori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xfffff911@.
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\item\instructionHeader{slli\ \ rd,rs1,imm}
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\label{insn:slli}
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Shift \verb@rs1@ left by the number of bits given in \verb@shamt_i@
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(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.
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For example, if \verb@x17@ = \verb@0x12345678@ then the instruction
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\verb@slli x12,x17,4@ will set \verb@x12@ to the value \verb@0x23456780@.
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\item\instructionHeader{slti\ \ rd,rs1,imm}
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\label{insn:slti}
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If the signed integer value in \verb@rs1@ is less than the
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signed integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@.
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Otherwise, set \verb@rd@ to \verb@0@.
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\item\instructionHeader{sltiu\ rd,rs1,imm}
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\label{insn:sltiu}
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If the unsigned integer value in \verb@rs1@ is less than the
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unsigned integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@.
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Otherwise, set \verb@rd@ to \verb@0@.
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Note that \verb@imm_i@ is always created by sign-extending the \verb@imm@ value
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as shown in \autoref{imm.i:decode} even though it is then later used as an unsigned
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integer for the purposes of comparing its magnitude to the unsigned value in rs1.
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Therefore, this instruction provides a method to compare \verb@rs1@ to a value
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in the ranges of
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$[\text{\tt 0}..\text{\tt 0x7ff}]$ and $[\text{\tt 0xfffff800}..\text{\tt 0xffffffff}]$.
|
||||
|
||||
\item\instructionHeader{srai\ \ rd,rs1,imm}
|
||||
\label{insn:srai}
|
||||
|
||||
Arithmetic-shift \verb@rs1@ right by the number of bits given in \verb@shamt_i@
|
||||
(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.
|
||||
|
||||
For example, if \verb@x17@ = \verb@0x87654321@ then the instruction
|
||||
\verb@srai x12,x17,4@ will set \verb@x12@ to the value \verb@0xf8765432@.
|
||||
|
||||
\item\instructionHeader{srli\ \ rd,rs1,imm}
|
||||
\label{insn:srli}
|
||||
|
||||
Logic-shift \verb@rs1@ right by the number of bits given in \verb@shamt_i@
|
||||
(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.
|
||||
|
||||
For example, if \verb@x17@ = \verb@0x87654321@ then the instruction
|
||||
\verb@srli x12,x17,4@ will set \verb@x12@ to the value \verb@0x08765432@.
|
||||
|
||||
\item\instructionHeader{xori\ \ rd,rs1,imm}
|
||||
\label{insn:xori}
|
||||
|
||||
Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@imm_i@.
|
||||
|
||||
For example, if \verb@x17@ = \verb@0x55551111@ then the instruction
|
||||
\verb@xori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ee@.
|
||||
|
||||
Recall that \verb@imm@ is sign-extended.
|
||||
Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction
|
||||
\verb@xori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xaaaae911@.
|
||||
|
||||
\end{itemize}
|
||||
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{S Type}
|
||||
@ -453,6 +773,65 @@ and converted as shown \autoref{Figure:imm_s_type_decode}.
|
||||
\index{imm\protect\_s}
|
||||
\end{figure}
|
||||
|
||||
\begin{itemize}
|
||||
\item\instructionHeader{sb\ \ \ \ rs2,imm(rs1)}
|
||||
\label{insn:sb}
|
||||
|
||||
Set the byte of memory at the address given by the sum of \verb@rs1@ and
|
||||
\verb@imm_s@ to the 8 \acrshort{lsb}s of \verb@rs2@.
|
||||
|
||||
For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
|
||||
if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@
|
||||
then the instruction \verb@sb x12,1(x13)@ will change the memory byte at address
|
||||
\verb@0x00002651@ from \verb@0x80@ to \verb@0x78@ resulting in:
|
||||
|
||||
\begin{verbatim}
|
||||
00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*
|
||||
00002650: 67 78 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *gx......val=....*
|
||||
00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*
|
||||
00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*
|
||||
00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*
|
||||
\end{verbatim}
|
||||
|
||||
\item\instructionHeader{sh\ \ \ \ rs2,imm(rs1)}
|
||||
\label{insn:sh}
|
||||
|
||||
Set the 16-bit half-word of memory at the address given by the sum of \verb@rs1@ and
|
||||
\verb@imm_s@ to the 16 \acrshort{lsb}s of \verb@rs2@.
|
||||
|
||||
For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
|
||||
if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@
|
||||
then the instruction \verb@sh x12,2(x13)@ will change the memory half-word at
|
||||
address \verb@0x00002652@ from \verb@0x0000@ to \verb@0x5678@ resulting in:
|
||||
|
||||
\begin{verbatim}
|
||||
00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*
|
||||
00002650: 67 80 78 56 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.xV....val=....*
|
||||
00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*
|
||||
00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*
|
||||
00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*
|
||||
\end{verbatim}
|
||||
|
||||
\item\instructionHeader{sw\ \ \ \ rs2,imm(rs1)}
|
||||
\label{insn:sw}
|
||||
|
||||
Set the 32-bit word of memory at the address given by the sum of \verb@rs1@ and
|
||||
\verb@imm_s@ to the 16 \acrshort{lsb}s of \verb@rs2@.
|
||||
|
||||
For example, given the memory contents shown in \autoref{Figure:imm:memory:dump},
|
||||
if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@
|
||||
then the instruction \verb@sw x12,0(x13)@ will change the memory word at address
|
||||
\verb@0x00002650@ from \verb@0x00008067@ to \verb@0x12345678@ resulting in:
|
||||
|
||||
\begin{verbatim}
|
||||
00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*
|
||||
00002650: 78 56 34 12 00 00 00 00 76 61 6c 3d 00 00 00 00 *xV4.....val=....*
|
||||
00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*
|
||||
00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*
|
||||
00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*
|
||||
\end{verbatim}
|
||||
|
||||
\end{itemize}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{B Type}
|
||||
@ -471,6 +850,60 @@ and converted as shown in \autoref{Figure:imm_b_type_decode}.
|
||||
\index{imm\protect\_b}
|
||||
\end{figure}
|
||||
|
||||
\begin{itemize}
|
||||
\item\instructionHeader{beq\ \ \ rs1,rs2,imm}
|
||||
\label{insn:beq}
|
||||
|
||||
If \verb@rs1@ is equal to \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\item\instructionHeader{bge\ \ \ rs1,rs2,imm}
|
||||
\label{insn:bge}
|
||||
|
||||
If the signed value in \verb@rs1@ is greater than or euqal to the
|
||||
signed value in \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\item\instructionHeader{bgeu\ \ \ rs1,rs2,imm}
|
||||
\label{insn:bgeu}
|
||||
|
||||
If the unsigned value in \verb@rs1@ is greater than or euqal to the
|
||||
unsigned value in \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\item\instructionHeader{blt\ \ \ rs1,rs2,imm}
|
||||
\label{insn:blt}
|
||||
|
||||
If the signed value in \verb@rs1@ is less than the
|
||||
signed value in \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\item\instructionHeader{bltu\ \ \ rs1,rs2,imm}
|
||||
\label{insn:bltu}
|
||||
|
||||
If the unsigned value in \verb@rs1@ is less than the
|
||||
unsigned value in \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\item\instructionHeader{bne\ \ \ rs1,rs2,imm}
|
||||
\label{insn:bne}
|
||||
|
||||
If \verb@rs1@ is not equal to \verb@rs2@ then add \verb@imm_b@ to the
|
||||
\verb@pc@ register.
|
||||
|
||||
\end{itemize}
|
||||
|
||||
%\label{insn:bgt}
|
||||
%\label{insn:ble}
|
||||
%\label{insn:bgtu}
|
||||
%\label{insn:beqz}
|
||||
%\label{insn:bnez}
|
||||
%\label{insn:blez}
|
||||
%\label{insn:bgez}
|
||||
%\label{insn:bltz}
|
||||
%\label{insn:bgtz}
|
||||
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{CPU Registers}
|
||||
\label{cpuregs}
|
||||
@ -497,41 +930,41 @@ in the compressed format.
|
||||
\begin{center}
|
||||
\begin{tabular}{|l|l|l|l|}
|
||||
\hline
|
||||
Reg & Alias & Description & Saved \\
|
||||
Reg & Alias & Description & Saved \\
|
||||
\hline
|
||||
\hline
|
||||
x0 & zero & Hard-wired zero & \\
|
||||
x1 & ra & Return address & \\
|
||||
x2 & sp & Stack pointer & yes \\
|
||||
x3 & gp & Global pointer & \\
|
||||
x4 & tp & Thread pointer & \\
|
||||
x5 & t0 & Temporary/alternate link register & \\
|
||||
x6 & t1 & Temporary & \\
|
||||
x7 & t2 & Temporary & \\
|
||||
x8 & s0/fp & Saved register/frame pointer & yes \\
|
||||
x9 & s1 & Saved register & yes \\
|
||||
x10 & a0 & Function argument/return value & \\
|
||||
x11 & a1 & Function argument/return value & \\
|
||||
x12 & a2 & Function argument & \\
|
||||
x13 & a3 & Function argument & \\
|
||||
x14 & a4 & Function argument & \\
|
||||
x15 & a5 & Function argument & \\
|
||||
x16 & a6 & Function argument & \\
|
||||
x17 & a7 & Function argument & \\
|
||||
x18 & s2 & Saved register & yes \\
|
||||
x19 & s3 & Saved register & yes \\
|
||||
x20 & s4 & Saved register & yes \\
|
||||
x21 & s5 & Saved register & yes \\
|
||||
x22 & s6 & Saved register & yes \\
|
||||
x23 & s7 & Saved register & yes \\
|
||||
x24 & s8 & Saved register & yes \\
|
||||
x25 & s9 & Saved register & yes \\
|
||||
x26 & s10 & Saved register & yes \\
|
||||
x27 & s11 & Saved register & yes \\
|
||||
x28 & t3 & Temporary & \\
|
||||
x29 & t4 & Temporary & \\
|
||||
x30 & t5 & Temporary & \\
|
||||
x31 & t6 & Temporary & \\
|
||||
x0 & zero & Hard-wired zero & \\
|
||||
x1 & ra & Return address & \\
|
||||
x2 & sp & Stack pointer & yes \\
|
||||
x3 & gp & Global pointer & \\
|
||||
x4 & tp & Thread pointer & \\
|
||||
x5 & t0 & Temporary/alternate link register & \\
|
||||
x6 & t1 & Temporary & \\
|
||||
x7 & t2 & Temporary & \\
|
||||
x8 & s0/fp & Saved register/frame pointer & yes \\
|
||||
x9 & s1 & Saved register & yes \\
|
||||
x10 & a0 & Function argument/return value & \\
|
||||
x11 & a1 & Function argument/return value & \\
|
||||
x12 & a2 & Function argument & \\
|
||||
x13 & a3 & Function argument & \\
|
||||
x14 & a4 & Function argument & \\
|
||||
x15 & a5 & Function argument & \\
|
||||
x16 & a6 & Function argument & \\
|
||||
x17 & a7 & Function argument & \\
|
||||
x18 & s2 & Saved register & yes \\
|
||||
x19 & s3 & Saved register & yes \\
|
||||
x20 & s4 & Saved register & yes \\
|
||||
x21 & s5 & Saved register & yes \\
|
||||
x22 & s6 & Saved register & yes \\
|
||||
x23 & s7 & Saved register & yes \\
|
||||
x24 & s8 & Saved register & yes \\
|
||||
x25 & s9 & Saved register & yes \\
|
||||
x26 & s10 & Saved register & yes \\
|
||||
x27 & s11 & Saved register & yes \\
|
||||
x28 & t3 & Temporary & \\
|
||||
x29 & t4 & Temporary & \\
|
||||
x30 & t5 & Temporary & \\
|
||||
x31 & t6 & Temporary & \\
|
||||
\hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
@ -585,6 +1018,7 @@ When XLEN is 64 or 128, the immediate value is sign-extended to the left.
|
||||
|
||||
\input{insn/lui.tex}
|
||||
|
||||
|
||||
%Instruction Format and Example:
|
||||
%
|
||||
%\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user