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pkgsrc-ng/lang/gcc45/patches/patch-gcc_config_rs6000_vector.md
Lionel Sambuc 612ad0a18c lang/gcc45
2016-01-22 00:09:29 +01:00

3.5 KiB
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NetBSD

--- gcc/config/rs6000/vector.md.orig Fri Feb 4 16:31:48 2011 +++ gcc/config/rs6000/vector.md @@ -441,27 +441,115 @@ "VECTOR_UNIT_ALTIVEC_P (mode)" "")

+(define_insn_and_split "*vector_uneq"

  • [(set (match_operand:VEC_F 0 "vfloat_operand" "")
  • (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
  •       (match_operand:VEC_F 2 "vfloat_operand" "")))]
  • "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "#"
  • ""
  • [(set (match_dup 3)
  • (gt:VEC_F (match_dup 1)
  •     (match_dup 2)))
  • (set (match_dup 4)
  • (gt:VEC_F (match_dup 2)
  •     (match_dup 1)))
  • (set (match_dup 0)
  • (not:VEC_F (ior:VEC_F (match_dup 3)
  •   	      (match_dup 4))))]
  • " +{
  • operands[3] = gen_reg_rtx (mode);
  • operands[4] = gen_reg_rtx (mode); +}")

+(define_insn_and_split "*vector_ltgt"

  • [(set (match_operand:VEC_F 0 "vfloat_operand" "")
  • (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
  •       (match_operand:VEC_F 2 "vfloat_operand" "")))]
  • "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "#"
  • ""
  • [(set (match_dup 3)
  • (gt:VEC_F (match_dup 1)
  •     (match_dup 2)))
  • (set (match_dup 4)
  • (gt:VEC_F (match_dup 2)
  •     (match_dup 1)))
  • (set (match_dup 0)
  • (ior:VEC_F (match_dup 3)
  •      (match_dup 4)))]
  • " +{
  • operands[3] = gen_reg_rtx (mode);
  • operands[4] = gen_reg_rtx (mode); +}")

+(define_insn_and_split "*vector_ordered"

  • [(set (match_operand:VEC_F 0 "vfloat_operand" "")
  • (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
  •          (match_operand:VEC_F 2 "vfloat_operand" "")))]
  • "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "#"
  • ""
  • [(set (match_dup 3)
  • (ge:VEC_F (match_dup 1)
  •     (match_dup 2)))
  • (set (match_dup 4)
  • (ge:VEC_F (match_dup 2)
  •     (match_dup 1)))
  • (set (match_dup 0)
  • (ior:VEC_F (match_dup 3)
  •      (match_dup 4)))]
  • " +{
  • operands[3] = gen_reg_rtx (mode);
  • operands[4] = gen_reg_rtx (mode); +}")

+(define_insn_and_split "*vector_unordered"

  • [(set (match_operand:VEC_F 0 "vfloat_operand" "")
  • (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
  •   	 (match_operand:VEC_F 2 "vfloat_operand" "")))]
  • "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "#"
  • ""
  • [(set (match_dup 3)
  • (ge:VEC_F (match_dup 1)
  •     (match_dup 2)))
  • (set (match_dup 4)
  • (ge:VEC_F (match_dup 2)
  •     (match_dup 1)))
  • (set (match_dup 0)
  • (not:VEC_F (ior:VEC_F (match_dup 3)
  •   	      (match_dup 4))))]
  • " +{
  • operands[3] = gen_reg_rtx (mode);
  • operands[4] = gen_reg_rtx (mode); +}")

;; Note the arguments for _builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select" [(set (match_operand:VEC_L 0 "vlogical_operand" "") (if_then_else:VEC_L (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")

  •   (const_int 0))

  •   (match_dup 4))
    (match_operand:VEC_L 2 "vlogical_operand" "") (match_operand:VEC_L 1 "vlogical_operand" "")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "")
  • "operands[4] = CONST0_RTX (mode);")

(define_expand "vector_select__uns" [(set (match_operand:VEC_L 0 "vlogical_operand" "") (if_then_else:VEC_L (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")

  •      (const_int 0))

  •      (match_dup 4))
    (match_operand:VEC_L 2 "vlogical_operand" "") (match_operand:VEC_L 1 "vlogical_operand" "")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
  • "")
  • "operands[4] = CONST0_RTX (mode);")

;; Expansions that compare vectors producing a vector result and a predicate, ;; setting CR6 to indicate a combined status