Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.
Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
On ADS5121 when booting linux the following errors are seen:
Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND
This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming. This patch
fixes this by being smarter about what to
fixup.
Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".
Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: John Rigby <jrigby@freescale.com>
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Support for the adsvix was originally provided by Applied Data
Systems (ADS), inc., now EuroTech, Inc.
The board never shipped aside from some sample boards.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor
on alchemy cpus.
Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.
Signed-off-by: Stefan Roese <sr@denx.de>
-This patchs gives support for the embbedded ppc440
on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by Stefan Roese
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors. Change the sense of detection so we
look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs. Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB. The hardware silently truncates
them so the code happens to work. This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Signed-off-by: Stefan Roese <sr@denx.de>
Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If
CFG_CSn_RO is defined as 0, the chipselect will not
be assigned.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Rename CONFIG_MCFTMR to CONFIG_MCFRTC to include real time
clock module in cpu/<cf arch>/cpu_init.c
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: Stefan Roese <sr@denx.de>
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: Stefan Roese <sr@denx.de>
