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typo

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This commit is contained in:
hneemann 2016-09-13 19:43:05 +02:00
parent 105fda8e56
commit 4eaee08f24
2 changed files with 2 additions and 2 deletions
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2
src/main/dig/test/JK-MS.dig
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@ -144,7 +144,7 @@
</testData>
</entry>
</elementAttributes>
<pos x="280" y="420"/>
<pos x="600" y="300"/>
</visualElement>
</visualElements>
<wires>

2
src/main/resources/lang/lang_en.xml
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@ -249,7 +249,7 @@ To analyse you can run the circuit in single gate step mode.</string>
<string name="lib_wires">Wires</string>
<string name="lib_test">Test</string>
<string name="menu_about">About</string>
<string name="menu_analyse">Analyse</string>
<string name="menu_analyse">Analysis</string>
<string name="menu_analyse_tt">Analyses the actual circuit</string>
<string name="menu_copy">Copy</string>
<string name="menu_custom">Custom</string>