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fixed a array index issue in the LUT hdl templates

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This commit is contained in:
hneemann 2019-03-03 15:27:10 +01:00
parent 21db168522
commit 8352fd2d76
3 changed files with 18 additions and 4 deletions
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10
src/main/resources/verilog/DIG_LookUpTable.v
View File

@ -32,8 +32,16 @@
initial begin<?
data := 0;
for (i := 0; i < lutSize; i++) { ?>
my_lut[<?= i ?>] = <?= format("%d'h%x", elem.Bits, elem.Data[i]) ?>;<?
my_lut[<?= i ?>] = <?
if (i<sizeOf(elem.Data)) {
data = elem.Data[i];
} else {
data = 0;
}
print(format("%d'h%x", elem.Bits, data));
?>;<?
} ?>
end
endmodule

8
src/main/resources/vhdl2/DIG_LookUpTable.tem
View File

@ -26,8 +26,14 @@ architecture Behavioral of <?=entityName?> is
maxCol:=76/(elem.Bits+4);
col:=0;
data:=0;
for (i:=0;i<len;i++) {
print( vhdl.value(elem.Data[i],elem.Bits));
if (i<sizeOf(elem.Data)) {
data = elem.Data[i];
} else {
data = 0;
}
print( vhdl.value(data,elem.Bits));
if (i<len-1) {
print(", ");
}

4
src/test/resources/dig/test/vhdl/lut2.dig
View File

@ -16,7 +16,7 @@
</entry>
<entry>
<string>Data</string>
<data>0,0,1,0,2,7,0,3</data>
<data>0,0,1,0,2,7</data>
</entry>
<entry>
<string>Inputs</string>
@ -83,7 +83,7 @@
1 0 0 0
1 0 1 7
1 1 0 0
1 1 1 3
1 1 1 0
</dataString>
</testData>
</entry>