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Author	SHA1	Message	Date
hneemann	3b78ea8433	added vhdl templates for subtract	2017-08-14 22:00:15 +02:00
hneemann	e9ddde0c73	typo	2017-08-14 18:52:49 +02:00
hneemann	327d3938ae	added vhdl for driver	2017-08-14 18:40:41 +02:00
hneemann	099d3fde32	added vhdl for driver	2017-08-14 18:33:47 +02:00
hneemann	0dea9effc3	fixed a findbugs issue	2017-08-14 16:36:11 +02:00
hneemann	ba0bf79dbf	fixed some findbugs issues	2017-08-14 16:28:38 +02:00
hneemann	cdb2eef854	added vhdl templates for async flip flops	2017-08-14 13:57:23 +02:00
hneemann	7827f6911c	moved vhdl integration test files	2017-08-14 12:57:11 +02:00
helmut.neemann	fbb8fba67c	added a BASYS3 vhdl example	2017-08-14 12:10:52 +02:00
helmut.neemann	d5ac9fb779	added system property for ghdl binary location	2017-08-14 11:13:22 +02:00
hneemann	14ba0c76c7	enabled VHDL export	2017-08-14 10:01:51 +02:00
hneemann	6e68b6a035	removed not needed var	2017-08-14 09:59:23 +02:00
hneemann	26c507d96a	fixed some naming issues	2017-08-14 09:54:35 +02:00
hneemann	6e184e9053	added vhdl test bench creation and ghdl integration tests	2017-08-13 21:09:30 +02:00
hneemann	f21a9dba22	added a test bench creator	2017-08-13 13:58:02 +02:00
hneemann	c1979dcff9	fixed a naming issue	2017-08-13 11:36:13 +02:00
hneemann	97fcef73ed	fixed an error in D-FF vhdl code	2017-08-13 00:21:34 +02:00
hneemann	33bf8d4ad7	fixed an error in D-FF vhdl code	2017-08-13 00:17:38 +02:00
hneemann	b1dda04f70	detects if names are used twice	2017-08-13 00:15:49 +02:00
hneemann	11a1acb239	detect invalid names	2017-08-13 00:02:17 +02:00
hneemann	4f83336849	deny vhdl export if circuit has errors	2017-08-12 23:01:53 +02:00
hneemann	e72becf527	added vhdl template for the register	2017-08-12 21:17:59 +02:00
hneemann	8242317eee	improved vhdl code	2017-08-12 20:53:37 +02:00
hneemann	65cba49d86	typo	2017-08-12 20:40:27 +02:00
hneemann	87ac14a1a7	added demux vhdl code	2017-08-12 20:36:53 +02:00
hneemann	d0d9a9453e	allow clock component in sub circuits	2017-08-12 15:25:58 +02:00
hneemann	584e82224e	fixed a bug in the clock divider	2017-08-12 12:56:58 +02:00
hneemann	d83c24b129	simplified vhdl output read avoiding	2017-08-12 11:09:47 +02:00
hneemann	cbf270b19a	added a clock divider to vhdl file	2017-08-11 23:42:02 +02:00
helmut.neemann	77d041a824	fixed some vivado issues	2017-08-11 16:29:14 +02:00
hneemann	b9cecb5bf6	added vivado constrains support	2017-08-11 14:03:28 +02:00
hneemann	632cb4bb13	updated release notes	2017-08-11 12:13:22 +02:00
hneemann	56c7608235	moved to non integer string pin numbers	2017-08-11 12:05:00 +02:00
hneemann	2414738949	added vhdl template for JK-flipflop	2017-08-11 08:52:50 +02:00
hneemann	00511cc9d0	avoids reading vhdl outputs	2017-08-10 13:04:09 +02:00
hneemann	ebec915217	added constants to vhdl	2017-08-10 11:42:38 +02:00
hneemann	03e6f9ab95	added comparator to vhdl lib	2017-08-10 10:04:04 +02:00
hneemann	cd4aa49faf	simplified adding of VHDL templates	2017-08-10 09:32:31 +02:00
hneemann	979487230e	added a vhdl template file reader	2017-08-09 22:22:26 +02:00
hneemann	5a48d2f20a	added decoder to vhdl export	2017-08-09 20:20:15 +02:00
hneemann	a08a28c3d7	added multiplexer vhdl export	2017-08-09 19:03:58 +02:00
hneemann	02089e1984	only white spaces	2017-08-09 16:40:58 +02:00
hneemann	9b9b4517e7	fixed some splitters issues	2017-08-09 15:17:10 +02:00
hneemann	aa2cf790e2	added splitters to vhdl generation	2017-08-09 13:59:38 +02:00
hneemann	20d8506997	refactoring of vhdl code generation	2017-08-09 11:52:09 +02:00
hneemann	bdacb81db4	added direct connection from input to output	2017-08-09 00:15:00 +02:00
hneemann	5e6a452d8b	fixed clock error	2017-08-08 23:10:05 +02:00
hneemann	e789f0f9f4	added generic vhdl	2017-08-08 22:59:52 +02:00
hneemann	1ea88ad0f7	minor simplifications	2017-08-08 19:34:13 +02:00
hneemann	488f603849	simplified handling of inverterConfig	2017-08-08 19:17:48 +02:00